Principal ASIC Design Engineer

TL;DR

Principal ASIC Design Engineer (Hardware): Architecting and implementing complex modules for high-performance networking chips with an accent on power, area, and performance optimization. Focus on RTL design, functional verification, and providing technical leadership for cross-functional teams.

Location: Hybrid role, requires working from an HPE office in California on average 2 days per week.

Salary: $174,000–$352,500 (Annual base salary in California).

Company

hirify.global is a global edge-to-cloud company focused on connecting, protecting, and analyzing data to drive innovation.

What you will do

• Architect complex modules and subsystems for high-performance networking chips.
• Develop detailed functional and micro-architecture specifications.
• Implement designs using Verilog or System Verilog.
• Write functional coverage and SVA to ensure robust verification.
• Collaborate with physical design teams to ensure timing closure and power efficiency.
• Provide technical leadership and mentorship to junior engineers and interns.

Requirements

• Bachelor’s degree in Electrical Engineering (Master’s strongly preferred).
• 15+ years of relevant experience in ASIC development.
• Strong coding proficiency in Verilog and System Verilog.
• Experience leading high-performance subsystems from specification to final netlist.
• Knowledge of synthesis, linting, and standard ASIC development tools.
• Excellent written and verbal communication skills.

Nice to have

• Knowledge of Computer Architecture and networking protocols.
• Proficiency in scripting languages such as Python or Perl.

Culture & Benefits

• Comprehensive health, financial, and emotional wellbeing benefits.
• Dedicated career development and professional growth programs.
• Inclusive work environment that values individual uniqueness and flexibility.
• Opportunities to work on high-impact, complex technical challenges.