Principal ASIC Design Engineer

Location: Onsite at an HPE office in the United States; the listed salary range applies to California

Salary: $174,000–$352,500 annual base salary in California, United States

Company

hirify.global is a global edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

• Architect complex modules and subsystems for high-performance networking chips.
• Define functional and micro-architecture specifications while meeting power, area, and performance targets.
• Implement designs in Verilog and SystemVerilog.
• Develop functional coverage and SVA to identify corner-case defects during verification.
• Apply power-reduction techniques and work with the physical design team on timing closure and frequency targets.
• Collaborate with verification engineers and provide technical guidance to junior engineers and interns.

Requirements

• Bachelor’s degree in Electrical Engineering and 15+ years of relevant experience; a Master’s degree is strongly desired.
• Demonstrated experience leading and implementing high-performance subsystems from specification through final netlist.
• Strong Verilog and SystemVerilog coding skills.
• Knowledge of computer architecture, networking protocols, synthesis, lint, and standard ASIC development tools.
• Strong analytical, problem-solving, written, and verbal communication skills.
• Knowledge of Perl or Python.

Culture & Benefits

• Health, financial, and emotional wellbeing benefits are available to employees and their families.
• Professional development programs support career growth and technical specialization.
• Inclusive workplace focused on collaboration, innovation, and individual differences.