ASIC Implementation Engineer PD (AI)

Location: San Jose, California, USA; in-person work required with no remote option

Annual base salary: USD 121,900–195,000

Company

hirify.global develops semiconductor products, including next-generation artificial intelligence and PCIe switch solutions.

What you will do

• Own chip floorplanning, partition creation, clock tree development, and top-level partition delivery.
• Resolve physical design issues related to chip integration and assembly.
• Coordinate top-level floorplanning, I/O and bump planning with package engineering.
• Develop and improve floorplan implementation methodologies using internal and industry tools.
• Evaluate vendors and IP and provide recommendations against design specifications.

Requirements

• Bachelor’s degree in Electrical Engineering with 8+ years of relevant experience, or a master’s degree with 6+ years of relevant experience.
• Experience with top-level floorplanning, die-size estimation, partitioning, clocking, and pin planning.
• Experience resolving chip-level DRC, LVS, and EMIR issues on advanced nodes.
• Experience with bump planning, RDL implementation, multi-voltage domains, hierarchical floorplanning, power grids, structured clocks, custom routing, and top-level pipeline planning.
• Experience with switch fabric, arbiter, high-speed DDR, SerDes, HBM, D2D I/O, or chiplet technologies.
• Experience scripting with Python, Tcl, or Perl and using EDA tools; ability to collaborate with design, package, and methodology teams.

Culture & Benefits

• Full-time employment with medical, dental, and vision coverage.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus and eligibility for new-hire and annual equity awards.
• Paid holidays, sick leave, vacation, family leave, and other applicable leaves of absence.
• Employee Assistance Program and an equal-opportunity employment environment.