ASIC Implementation Engineer PD

TL;DR

ASIC Implementation Engineer PD (ASIC/Physical Design): Own chip floor planning and top-level physical design execution from RTL to silicon tape-out with an accent on clock tree delivery, partitioning, and I/O/bump planning. Focus on resolving advanced-node physical design issues (DRC/LVS/EMIR), improving floorplan implementation methodologies, and evaluating vendors/IP to meet design specifications.

Company

hirify.global develops semiconductor and infrastructure technology for advanced computing and networking.

What you will do

• Own chip floor planning, partition creation, clock tree, and delivery of top-level partitions.
• Resolve physical design issues related to chip integration and assembly.
• Manage cross-functional interactions for top-level floorplanning, I/O, and bump planning with the package team.
• Develop and improve floorplan implementation methodologies using industry and internal tools.
• Perform technical evaluations of vendors and IP and provide recommendations to meet design specifications.

Requirements

• In-person work required at the San Jose site; no remote work option.
• Bachelor’s in Electrical Engineering with 8+ years of top-level floorplanning experience, or Master’s with 6+ years (die size estimate, partitioning, clocking, pin planning).
• Experience across multiple technologies such as Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, or chiplet.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes.
• Proven experience with bump planning, RDL implementation, and multi-voltage domain designs.
• Experience with scripting languages (Python, Tcl, or Perl) and EDA tools.

Culture & Benefits

• Annual base salary range: USD 121,900–195,000.
• Discretionary annual bonus and potential new hire equity grant and annual equity awards.
• Medical, dental, and vision plans; 401(K) participation with company matching; ESPP.
• Paid holidays, paid sick leave, and vacation time; paid family leave and other leaves per applicable laws.