R&D Engineer IC Design 4

Location: San Jose, California, United States

Annual base salary: USD 121,900–195,000, plus discretionary bonus and equity awards.

Company

hirify.global develops semiconductor and technology solutions.

What you will do

• Define architectures and design logic blocks from system requirements.
• Develop, synthesize, and constrain RTL designs for ASIC or standard product implementations.
• Verify designs through Verilog simulation, debugging, lint, and formal verification.
• Analyze timing from physical implementation and support timing closure for high-frequency designs.
• Perform RTL and gate-level power analysis and apply DFT and scan methodologies.
• Collaborate independently and within large teams spanning multiple geographies.

Requirements

• BS or MS degree in Electrical or Computer Engineering, or equivalent experience.
• 8+ years of related experience with a bachelor's degree, or 6+ years with a master's degree.
• Experience with the complete ASIC or standard product implementation flow, including RTL synthesis and timing analysis/closure.
• Proficiency with TCL or Perl scripting, Synopsys Design Compiler/DC Topo or Cadence RTL Compiler, and Primetime.
• Knowledge of Liberty LIB timing models, Formality or Conformal, SpyGlass Lint, power analysis, DFT, scan methodology, and version control.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leaves.
• Employee Assistance Program, annual bonus eligibility, and equity opportunities.