R&D Engineer IC Design (ASIC)

TL;DR

R&D Engineer IC Design (ASIC): Responsible for front-end design and verification of design blocks with an accent on architecture definition, logic design, and synthesis. Focus on ensuring timing closure, formal verification, and power analysis across the complete ASIC implementation flow.

Location: Must be based in San Jose, USA

Salary: $121,900 – $195,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Define architecture and perform logic design for complex design blocks.
• Execute synthesis, constraint development, and timing analysis.
• Conduct design verification through simulation and formal verification methods.
• Analyze timing from physical implementation and perform power analysis on RTL and gate-level netlists.
• Collaborate with large, geographically distributed teams to ensure design success.

Requirements

• Must be based in San Jose, USA
• BS/MS in Electrical or Computer Engineering or equivalent.
• 8+ years of related experience with a Bachelor's degree, or 6+ years with a Master's degree.
• Proficiency in ASIC implementation flow including RTL synthesis and timing closure.
• Experience with TCL/Perl scripting and design tools like Synopsys Design Compiler or Cadence RTL Compiler.
• Knowledge of formal verification, Spyglass Lint, and DFT/scan methodology.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and annual equity awards.
• Discretionary annual bonus eligibility.
• Paid holidays, sick leave, and vacation time.