R&D Engineer IC Design 4 (ASIC)

Location: San Jose, California, USA; onsite role

Annual base salary: USD 121,900–195,000

Company

hirify.global is the hiring company for this ASIC IC design position.

What you will do

• Define architectures and design logic blocks from systems requirements documents.
• Perform RTL/front-end design, synthesis, constraint development, and timing analysis.
• Verify designs through Verilog simulation, debugging, and formal verification.
• Analyze timing from physical implementation for high-frequency designs and advanced technology nodes and libraries.
• Perform RTL and gate-level netlist power analysis and apply DFT and scan methodologies.
• Work independently and collaborate with a large team spanning multiple geographies.

Requirements

• BS or MS degree in Electrical Engineering, Computer Engineering, or an equivalent qualification.
• Bachelor’s degree with 8+ years of related experience, or a Master’s degree with 6+ years of related experience.
• Experience with the complete ASIC or standard product implementation flow, including RTL synthesis and timing analysis/closure.
• Familiarity with the complete ASIC design and implementation flow.
• Proficiency with TCL or Perl scripting and version control systems such as SVN or Git.
• Experience with Synopsys Design Compiler/DC Topo or Cadence RTL Compiler.
• Experience with PrimeTime timing analysis for high-frequency designs and advanced technology nodes/libraries.
• Understanding of Liberty LIB timing models.
• Experience with Synopsys Formality or Cadence Conformal, SpyGlass Lint, RTL and gate-level power analysis, and DFT/scan methodology.

Culture & Benefits

• Full-time employment with medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus, competitive new-hire equity grant, and potential annual equity awards.
• Paid holidays, paid sick leave, vacation time, paid family leave, and other applicable leaves of absence.
• Employee Assistance Program.