Engineer II - Design (ASIC)

Location: Hauppauge, New York, United States; onsite

Annual base salary: $70,304–$143,000 USD

Company

hirify.global is a global semiconductor company developing embedded controller solutions and processor-based products.

What you will do

• Develop RTL for processor-based ASIC and System-on-Chip products used in tablets, notebooks, and embedded systems.
• Apply SoC design methodologies including design entry, simulation, synthesis, timing closure, and pre-silicon FPGA emulation.
• Perform formal verification, RTL and gate-level implementation, cross-domain clocking analysis, and static timing analysis.
• Design complex state machines and datapath logic.
• Generate test vectors and collaborate with the ASIC design team.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering.
• 3–5 years of experience in RTL design for ASIC implementation.
• Experience with design entry, synthesis, formal verification, RTL/gate-level implementation, cross-domain clocking analysis, and static timing analysis tools.
• Practical experience with static timing analysis and Verilog simulation tools.
• Knowledge of Verilog/SystemVerilog, VHDL, and programming languages such as C, Python, Perl, or TCL.
• Legal right to work in the United States is required.

Nice to have

• Coursework in microelectronic devices and circuits, semiconductor devices, analog and digital integrated circuits, digital signal processing, and low-power VLSI techniques.

Culture & Benefits

• Mentorship and access to structured leadership and career development programs.
• Health benefits beginning on the first day.
• Retirement savings plans and an employee stock purchase plan with a two-year look-back feature.
• Restricted stock units and quarterly bonus payments as part of the total compensation package.
• Travel expectation of 0%–25%; the role involves primarily sitting with occasional standing or walking.