обновлено 4 дня назад
Design Verification Engineer (ASIC)
143 800 - 230 000$
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Описание вакансии
Текст:
TL;DR
Design Verification Engineer (ASIC): Developing verification models, environments, test cases, and coverage strategies for complex digital and mixed-signal IP blocks with an accent on SystemVerilog, UVM, SVA, and RTL/gate-level debugging. Focus on building scalable verification architectures, analyzing simulation failures, closing coverage, and supporting emulation and FPGA prototyping for ASIC development.
Location: Broomfield, Colorado, United States. Onsite role with legal authorization to work in the United States required.
Annual base salary: USD 143,800–230,000, plus discretionary bonus and equity opportunities.
Company
's ASIC Products Division develops complex custom ASICs and embedded IP for digital and mixed-signal applications.
What you will do
- Define verification plans, environment architectures, test cases, and testbench components for complex digital and mixed-signal IP blocks.
- Develop functional models, UVM agents, checkers, behavioral models, random and directed tests, and SystemVerilog Assertions.
- Analyze coverage, drive coverage closure, and debug RTL- and gate-level simulation failures.
- Support block-, system-, and ASIC-level verification, including emulation and FPGA prototyping platforms.
- Evaluate and adopt advanced verification methodologies and flows in collaboration with design teams and EDA vendors.
Requirements
- 12+ years of verification experience for complex digital and mixed-signal circuits, or 10+ years with an MS degree.
- Strong experience with SystemVerilog, UVM, SVA, RTL, gate-level netlists, SDF, and verification at block and system levels.
- Experience with mixed-signal components such as PLLs, DLLs, ADCs, and DACs, including schematic analysis and debug.
- Experience with Synopsys, Cadence, and Mentor simulation tools, plus Perl, Python, Tcl, or similar scripting languages.
- Experience with version control systems such as DesignSync or Git and with developing reusable, scalable verification environments.
- BS or MS in Electrical Engineering or Computer Engineering and legal authorization to work in the United States.
Nice to have
- Hardware design and debug experience.
- Experience with Palladium, Veloce, Zebu, or Xilinx FPGA platforms.
- Formal verification, co-simulation, or iJTAG verification using ICL and PDL in Tessent.
Culture & Benefits
- Work independently and with global teams in a dynamic, highly visible environment.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation, family leave, and other applicable leave programs.
- Discretionary annual bonus, competitive new-hire equity grant, and annual equity awards.
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