1 день назад
Lead Analog Layout Design Engineer (SerDes)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Lead Analog Layout Design Engineer (SerDes/UCIe) (Analog/Mixed-Signal IC Design): Designing high-speed SerDes layouts for UCIe products at data rates up to 64 Gbps and on technology nodes such as 2nm FinFET CMOS with an accent on analog/mixed-signal circuit blocks, floor planning, detailed layout, and final verification. Focus on leading layout from block level through PHY top-level integration, signing off high-speed IP, and collaborating across US time zones.
Location: Cork, Ireland. Collaboration with global teams in US West Coast and East Coast time zones is required. Travel: >10%.
Company
develops electronic design software, hardware, and IP for products ranging from chips and boards to complete systems.
What you will do
- Design high-speed SerDes for UCIe products at data rates up to 64 Gbps on leading-edge technology nodes, including 2nm FinFET CMOS.
- Create high-quality analog and mixed-signal layouts in collaboration with circuit designers.
- Manage the back-end flow from initial floor planning through detailed layout and final foundry design-rule verification.
- Provide technical leadership from block-level layout through PHY top-level integration and sign-off.
- Collaborate with layout designers, circuit designers, and project managers across global teams to deliver IP and test chips.
Requirements
- Minimum 7 years of experience in CMOS SerDes or high-speed I/O IC layout design and development.
- Layout experience with several SerDes circuit blocks, including drivers, receivers, serializers, deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias and bandgap circuits, and voltage regulators.
- Experience implementing high-speed, high-accuracy cells, blocks, and IP blocks efficiently and to a high quality standard.
- Excellent problem-solving skills, analog aptitude, communication skills, and ability to work cooperatively in a team environment.
- BEng, MEng, or PhD.
Nice to have
- tool experience and design experience above 10 Gbps and in technologies below 16nm.
- Experience collaborating with Virtuoso and PVS R&D developers on layout editing and verification tools.
- Interest in evolving analog and custom layout design practices.
Culture & Benefits
- Work with global product, design, and R&D teams.
- Contribute to electronic design technologies used in consumer, hyperscale computing, 5G, automotive, aerospace, industrial, and healthcare applications.
- Equal employment opportunity and employment equity are supported throughout the organization.
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