Principal SerDes Architect (Analog Circuit Design)

TL;DR

Principal SerDes Architect (Analog Circuit Design): Leading the architecture and development of next-generation high-speed IO PHYs with an accent on power, performance, and area (PPA) metrics. Focus on optimizing analog circuits in advanced process nodes and defining technical strategies for industry-leading mixed-signal IPs.

Location: Hybrid (US: Santa Clara, Phoenix, Folsom, or Hillsboro)

Salary: $220,920 - $311,890 USD

Company

Global leader in semiconductor innovation and advanced analog/mixed-signal IP development.

What you will do

• Lead architecture definition and development of next-generation high-speed IO PHYs with industry-leading PPA metrics.
• Design and optimize analog circuits, including TX/RX blocks, in advanced process nodes.
• Create floorplans, extract chip parameters, and simulate analog behavior models.
• Develop comprehensive test plans and verify designs against microarchitecture specifications.
• Provide technical leadership and align technical strategies with organizational goals.
• Mentor other technical leaders and cultivate a community of technical excellence.

Requirements

• Bachelor's in Electrical Engineering (12+ years exp) or Master's (10+ years exp).
• Deep expertise in analog circuit design fundamentals, I/O PHY architecture, and low-power design.
• Proficiency in analog behavior modeling and circuit simulation techniques.
• Demonstrated experience in advanced process nodes and mixed-signal design.
• Must be based in the United States.

Nice to have

• Familiarity with SerDes fundamentals, UCIe, and PCIe specifications.
• Proven track record of technical leadership influencing industry-wide direction.
• Strong strategic thinking and problem-solving skills.

Culture & Benefits

• Hybrid work model allowing split time between on-site and off-site.
• Competitive total compensation package including stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.