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2 дня назад

Layout Design Intern (Fall 2026)

25 - 35CAD
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Layout Design Intern (Fall 2026) (Analog/Mixed-Signal Layout): Developing custom layouts for advanced high-speed analog and mixed-signal circuit blocks in optical fiber transmission products with an accent on floorplanning, device matching, parasitic minimization, and physical verification. Focus on debugging DRC and LVS reports, analyzing electromigration and IR drop, and identifying layout-related risks with circuit designers.

Location: Ottawa, Canada

Hourly pay: CAD 25.50–35.00

Company

A technology company developing high-speed connectivity infrastructure and optical fiber transmission solutions for the telecommunications industry.

What you will do

  • Conduct layout feasibility studies with senior analog designers and evaluate design trade-offs for high-speed circuits.
  • Develop custom layouts for advanced analog and mixed-signal blocks using structured floorplanning, placement, and routing methods.
  • Perform physical verification, including DRC, LVS, electromigration, and IR drop analysis.
  • Explore layout tool features, design flows, and processes to improve efficiency and productivity.
  • Collaborate with circuit designers and layout engineers to identify and resolve layout risks early.
  • Provide status updates and participate in design discussions, team meetings, and knowledge-sharing activities.

Requirements

  • Currently enrolled in an Electrical Engineering or related degree program.
  • Hands-on experience with custom analog and mixed-signal layout design in deep sub-micron CMOS technologies.
  • Strong knowledge of floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations.
  • Experience creating custom layouts for analog or mixed-signal blocks such as operational amplifiers or current mirrors.
  • Familiarity with semiconductor manufacturing processes, foundry design rules, Cadence Virtuoso, and Siemens Calibre.
  • Ability to interpret and debug DRC and LVS reports.

Nice to have

  • Exposure to high-speed data converter or PLL layout design.
  • Familiarity with BiCMOS technologies.
  • Scripting experience with Perl or SKILL for layout automation and productivity improvements.
  • Experience working in cross-functional hardware design teams.
  • Strong analytical skills and the ability to identify layout-sensitive circuit structures.

Culture & Benefits

  • Four-month full-time work term starting in September or October 2026.
  • Collaborative engineering environment with opportunities for hands-on work and knowledge sharing.
  • Employee Assistance Program access for students.
  • Company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.
  • Inclusive workplace committed to respect, diversity, and equal opportunity.

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