Analog Layout Design Engineer (Semiconductors)

TL;DR

Analog Layout Design Engineer (Semiconductors): Designing and optimizing complex layouts for analog signal circuits with an accent on performance, area, and reliability. Focus on floor planning, executing design verification checks (DRC, IR, EM), and implementing innovative layout methodologies.

Location: Hybrid (US: Hillsboro, OR or Austin, TX)

Salary: $122,440 – $172,860 USD

Company

hirify.global is a global leader in semiconductor innovation, developing cutting-edge processors and technologies that power diverse industries worldwide.

What you will do

• Design complex layouts of analog signal circuits based on detailed design specifications.
• Conduct comprehensive design verification checks, including process design rules, electromigration, voltage drop (IR), and ESD.
• Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet electrical requirements.
• Perform detailed signal planning for complex analog circuits, optimizing for area, power, and performance.
• Drive the development and implementation of innovative layout methodologies to improve quality and productivity.
• Collaborate with cross-disciplinary teams including analog circuit design and process technology.

Requirements

• Bachelor's degree in Electrical/Computer Engineering with 3+ years of experience, or a Master's degree with 2+ years of experience.
• Strong fundamentals in analog device and metal layout, including analog/mixed-signal principles.
• Proficiency with Cadence Virtuoso Layout Suite and Calibre/ICV DRC.
• Experience with CMOS technologies and high-voltage rules.
• Proven experience in floor planning and hierarchical layout planning for analog blocks.
• Must be authorized to work in the United States.

Nice to have

• Deep understanding of mismatch, parasitics, IR drop, and electromigration impacts on circuit performance.
• Experience applying common-centroid, interdigitation, and symmetry-based layout practices.
• Ability to evaluate and mitigate process variations and gradient effects.
• Experience in parasitic-aware design and correlation of LVS, DRC, and silicon behavior.
• Skills in optimizing layouts for noise isolation, shielding, and signal integrity.

Culture & Benefits

• Opportunity to work on cutting-edge semiconductor technologies and learn from experienced mentors.
• Competitive total compensation package including stock bonuses.
• Comprehensive benefits programs covering health, retirement, and vacation.
• Collaborative and inclusive engineering culture focused on technical development.
• Hybrid work model allowing a split between on-site and off-site work.