Analog Layout Design Engineer (Semiconductor)

Location: United States, with a hybrid work model requiring time on-site at an assigned hirify.global site. Primary location: Hillsboro, Oregon; additional location: Austin, Texas.

Annual salary: $122,440–$172,860 USD, depending on location, skills, experience, and education.

Company

hirify.global develops semiconductor technologies and provides engineering solutions for businesses and industries.

What you will do

• Design complex analog and mixed-signal circuit layouts from detailed specifications.
• Perform DRC, electromigration, IR drop, ESD, and other reliability verification checks.
• Develop floorplans, power grids, ESD structures, bump layouts, and detailed signal plans.
• Optimize layouts for area, power, reliability, performance, noise isolation, shielding, and signal integrity.
• Develop analog layout methodologies and troubleshoot design tools, flows, and methodology issues.
• Collaborate with circuit design, process technology, package design, extraction, and simulation teams to resolve tradeoffs and meet specifications.

Requirements

• Bachelor’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field with 3+ years of experience, or a relevant master’s degree with 2+ years of experience.
• Experience with analog device and metal layout fundamentals, analog/mixed-signal concepts, CMOS technologies, and high-voltage rules.
• Experience using Cadence Virtuoso Layout Suite and Calibre or ICV DRC for design and verification.
• Experience with floorplanning and hierarchical layout planning for analog and mixed-signal blocks.
• Experience conducting layout performance verification and debugging layout-related issues.
• Strong collaboration, communication, problem-solving, attention to detail, accountability, and learning agility.

Nice to have

• Knowledge of mismatch, parasitics, IR drop, electromigration, coupling, process variation, and gradient effects.
• Experience applying common-centroid, interdigitation, and symmetry-based layout techniques.
• Experience with parasitic-aware design, extraction data such as xtract or SPEF, and simulation collaboration.
• Ability to correlate LVS, DRC, extraction, and silicon behavior during debugging.

Culture & Benefits

• Work on advanced semiconductor technologies in a collaborative and inclusive engineering environment.
• Access to experienced engineers, mentors, career growth, and technical development opportunities.
• Hybrid work model combining on-site and off-site work.
• Competitive compensation with stock bonuses, health benefits, retirement programs, and vacation.