Analog Layout Engineer (FinFET Technology)

Location: Hybrid work in Portugal, with locations in Fundão, Lisboa - Expo, or VNG - Cais Gaia

Company

hirify.global Engineering provides R&D, engineering, digital, and software services to innovative companies across multiple industries.

What you will do

• Develop analog layouts for amplifiers, references, bias blocks, and data converters in FinFET nodes.
• Drive DRC/LVS closure and debug advanced design-rule issues efficiently.
• Perform EM/IR analysis and implement changes to meet reliability targets.
• Control parasitic effects through routing, shielding, extraction, and post-extraction corrections.
• Apply common-centroid, interdigitation, and dummy-device matching techniques for precision circuits.
• Collaborate with circuit designers to optimize performance, yield, and manufacturability while meeting SADP/SAQP constraints.

Requirements

• At least 5 years of hands-on experience designing FinFET layouts for analog IP development.
• Strong knowledge of LDE effects, including WPE, STI, and LOD, and their mitigation strategies.
• Proficiency with Cadence Virtuoso, Calibre, and PVS.
• Experience with parasitic extraction flows, correlation techniques, EM/IR verification, and sign-off.
• Understanding of BTI, HCI, guard-banding, advanced-node design rules, and color-aware layout.
• Ability to automate layout tasks using SKILL or Python scripts.

Culture & Benefits

• Multicultural and inclusive work environment.
• Supportive atmosphere focused on work-life balance.
• Career growth programs, training, and certifications in advanced technologies.
• Opportunities to work on national and international engineering projects.
• Health and life insurance.
• Referral program with bonuses and access to modern office locations.