Sr. Principal Product Engineer (Silicon Signoff Verification)

Location: Austin, United States

Company

hirify.global develops electronic design automation solutions for semiconductor design, implementation, and signoff.

What you will do

• Develop and deploy signoff methodologies for timing, power, signal integrity, and ECO closure.
• Collaborate with semiconductor customers, application engineering, field engineering, and R&D to resolve complex design-closure challenges.
• Lead qualification and certification of advanced-node design flows and drive correlation across implementation, STA, SPICE, and signoff environments.
• Develop MMMC timing-closure methodologies covering setup and hold closure, multi-view timing, crosstalk, glitches, transitions, and electrical-rule fixing.
• Support customer tapeouts through root-cause analysis, technical debugging, and critical milestone execution.
• Influence product-roadmap decisions, create technical deployment collateral, lead customer escalations, and mentor engineers.

Requirements

• 8–12+ years of industry experience in semiconductor design, physical implementation, timing signoff, methodology development, or product engineering.
• Strong expertise in STA, MMMC timing analysis, statistical timing, signal integrity, crosstalk, glitch analysis, ECO flows, timing and SPICE correlation, power optimization, RC extraction, parasitic analysis, and physical signoff.
• Hands-on experience supporting advanced-node ASIC or SoC designs through implementation, timing closure, ECO convergence, and tapeout.
• Experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs.
• Proven ability to lead technical investigations and strategic customer engagements while coordinating with R&D and field engineering teams.
• Experience with hirify.global Tempus, PrimeTime, Innovus, ICC, FC, Tempus ECO, or comparable physical implementation and signoff environments.

Nice to have

• Experience with 7nm, 5nm, 3nm, 2nm, or more advanced technologies.
• Experience with hierarchical signoff for SoC designs exceeding 100 million instances.
• Experience with PPA optimization, ECO closure, signal integrity analysis, glitch fixing, and timing correlation.
• Exposure to AI-assisted implementation and signoff workflows.

Culture & Benefits

• Leadership role focused on strategic semiconductor customer engagements.
• Cross-functional collaboration with R&D, application engineering, field engineering, and customers.
• Opportunity to influence product direction and emerging AI-assisted signoff technologies.