обновлено 5 дней назад
Director, Silicon Design Engineering (Physical Design Timing)
220 920 - 311 890$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Director, Silicon Design Engineering (Physical Design Timing): Delivering next-generation SoC designs through timing analysis, constraint generation, clocking methodology, and power-performance optimization with an accent on high-performance, low-power physical design. Focus on developing timing models and clocking flows, resolving chip- and block-level timing violations, and integrating complex designs across architecture, logic, and clocking teams.
Location: Hybrid work model with on-site work at assigned sites in Santa Clara, California; Hillsboro, Oregon; or Austin, Texas, United States
Annual salary: $220,920–$311,890 USD
Company
's Central Engineering Group develops scalable engineering solutions for product enablement, custom ASICs, and foundry enablement across the company's semiconductor businesses.
What you will do
- Perform timing analysis and optimization for high-performance, power-efficient SoC designs.
- Generate and validate timing constraints and resolve chip- and block-level timing violations.
- Develop timing models, physical design methodologies, and automation flows.
- Define process, voltage, and temperature conditions for timing analysis, product operating plans, and binning requirements.
- Collaborate with architecture, logic design, clocking, and full-chip teams to balance clock networks and optimize power delivery and partitioning.
- Drive advanced SoC clocking flows and low-power clock network guidelines through chip integration.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
- At least 12 years of relevant experience with a bachelor's degree, 8 years with a master's degree, or 6 years with a PhD.
- Strong experience with static timing analysis, timing constraint generation, and timing optimization.
- Knowledge of SoC clocking, timing budgeting, constraint adaptation, digital design, and power-performance analysis.
- Experience with physical design tools, flows, methodologies, advanced process nodes, and EDA tools.
- Familiarity with TCL or similar scripting languages for automation and design optimization.
Nice to have
- Experience with signal integrity and power integrity analysis.
- Experience collaborating across architecture, logic design, and clocking teams on large-scale designs.
Culture & Benefits
- Hybrid work model combining on-site and off-site work.
- Competitive pay with stock bonuses.
- Health, retirement, and vacation benefits.
- Position of Trust requiring consent to and completion of an extended background investigation.
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