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20 часов назад

Director, Silicon Design Engineering (Physical Design)

220 920 - 311 890$
Формат работы
hybrid
Тип работы
fulltime
Грейд
director
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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TL;DR

Director, Silicon Design Engineering (Physical Design): Leading the delivery of next-generation SoC products with an accent on timing analysis, power efficiency, and performance optimization. Focus on driving advanced methodologies, collaborating with cross-functional architecture and clocking teams, and ensuring high-performance silicon integration.

Location: Must be based in the US (Santa Clara, CA; Hillsboro, OR; or Austin, TX). This role follows a hybrid work model.

Salary: $220,920–$311,890 USD

Company

hirify.global is a global leader in semiconductor technology, building scalable engineering solutions across product enablement, custom ASIC, and foundry services.

What you will do

  • Perform comprehensive timing analysis and optimization to ensure robust, high-performance SoC designs.
  • Generate and validate timing constraints while addressing violations at chip and block levels.
  • Develop and implement methodologies to produce high-quality timing models for the physical design team.
  • Define PVT conditions tailored to product operating plans and binning requirements.
  • Collaborate with clocking and logic design teams to optimize power delivery, partitioning, and clock network balance.
  • Drive flow development for seamless chip integration and adherence to low-power guidelines.

Requirements

  • Must be based in the US (eligible for hybrid work at hirify.global sites).
  • Bachelor's degree in Electrical or Computer Engineering (or related field).
  • 12+ years of experience (with Bachelor's), 8+ years (with Master's), or 6+ years (with PhD) in timing analysis or physical design.
  • Proficiency in static timing analysis, constraint generation, and optimization techniques.
  • Strong knowledge of SoC clocking, timing budgeting, and scripting (TCL).
  • Experience with physical design tools, flows, and methodologies (TFM).

Nice to have

  • Exposure to signal and power integrity analysis.
  • Experience with advanced process nodes and industry-leading EDA tools.
  • Proven ability to lead and collaborate with cross-functional architecture and logic design teams.

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Hybrid work model allowing flexibility between on-site and off-site work.
  • Opportunity to work on cutting-edge semiconductor innovations with global impact.

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