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3 дня назад

Sr. Staff PCB Design Engineer (AI Accelerators)

175 000 - 265 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Sr. Staff PCB Design Engineer (AI Accelerators): Leading the physical design of high-complexity, high-layer-count PCBAs for AI accelerator cards and system baseboards with an accent on high-speed signal integrity, power delivery, and scalable layout methodology. Focus on routing 112G/224G SerDes, PCIe Gen5/6, CXL, DDR5/HBM, automating design audits, and meeting DFM, DFT, and DFA requirements for high-yield production.

Location: Santa Clara, United States; hybrid work arrangement.

Salary: $175,000–$265,000 per year, plus equity and bonus opportunities.

Company

hirify.global develops software and hardware solutions for generative AI, including AI accelerator platforms.

What you will do

  • Lead full-cycle PCB layout for high-complexity AI accelerator cards and system baseboards.
  • Architect and manage Cadence Allegro Constraint Manager hierarchies for high-speed routing rules and electrical constraints.
  • Develop SKILL, Python, or TCL automation for layout tasks, DRC checks, and reporting.
  • Execute layout for PCIe Gen5/6, CXL, and custom die-to-die interconnects, while supporting signal integrity and power delivery.
  • Define PCB stack-ups using low-loss materials and hybrid build-ups, and collaborate with power, ASIC, and manufacturing teams.
  • Coordinate with fabricators and contract manufacturers on DFM, DFT, and DFA requirements for high-yield production.

Requirements

  • Bachelor’s degree in Electrical or Electronic Engineering, or equivalent practical experience.
  • 10+ years of high-speed, high-density PCB layout experience for servers, networking, or AI accelerators.
  • Proficiency with Cadence Allegro Constraint Manager, including T-junctions, differential-pair phase tuning, and Z-axis delay matching.
  • Ability to write and deploy SKILL scripts or use the Allegro API for design audits and layout automation.
  • Deep knowledge of back-drilling, via-in-pad, skip-vias, HDI, and ELIC design.
  • Experience routing 112G SerDes and complex DDR5/HBM interfaces.

Nice to have

  • Experience establishing library management systems and standardized footprint and padstack processes.
  • Familiarity with PLM/PDM integration, layout releases, and ECO workflows.
  • Knowledge of PCB warpage mitigation for large-form-factor ASICs and MCMs.

Culture & Benefits

  • Respectful, collaborative, and inclusive working environment.
  • Direct communication and emphasis on humility, execution, and continuous learning.
  • Medical, dental, and vision coverage.
  • 401(k) and an incentive plan with equity and performance-based bonus opportunities.

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