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2 дня назад

Signal & Power Integrity Engineer (AI)

150 000 - 275 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Signal & Power Integrity Engineer (AI): Designing and optimizing signal and power integrity for an AI accelerator platform across silicon, advanced packages, boards, and racks with an accent on high-speed 112G/224G signaling, power delivery networks, and 2.5D/3D packaging. Focus on closing DC and dynamic IR drop and impedance targets, assigning C4/BGA balls, and correlating SI/PI test vehicles with silicon measurements during bring-up.

Location: On-site in San Jose, California. Relocation support is available for candidates moving to San Jose.

Base salary: $150,000–$275,000 per year, plus equity.

Company

hirify.global builds hardware for frontier AI inference, co-designing chips, racks, software, and manufacturing systems to optimize throughput and latency.

What you will do

  • Analyze and optimize signal integrity and power integrity across 2D, 2.5D, and 3D packages.
  • Drive high-speed 112G/224G routing requirements into interposer and substrate layouts through tape-out.
  • Own power delivery network design, decoupling strategy, DC and dynamic IR drop, and impedance targets across all rails.
  • Manage ball map, C4, and BGA pin assignments through final freeze with package, ASIC, and board teams.
  • Support board- and rack-level SI/PI topology studies, test vehicle design, and cable characterization.
  • Collaborate with silicon, package, platform, system, OSAT, and ODM teams through design reviews.

Requirements

  • 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience defining and closing PDNs for high-power silicon, including substrate and PCB plane design, decoupling, and dynamic IR/EM analysis.
  • Experience with HBM, SerDes, and die-to-die interfaces, as well as CoWoS or equivalent advanced packaging technologies.
  • Hands-on expertise with ANSYS HFSS or SIwave, Cadence Sigrity, or Keysight ADS.
  • Strong analytical and communication skills, including presenting risks, sign-off status, and trade-offs to cross-functional leadership.

Nice to have

  • Familiarity with RTL-to-GDSII context and package-board PDN interactions.
  • Experience with multi-die, 2.5D, or 3D packaging sign-off and chip-package-system co-design.
  • Project management experience with internal teams, OSAT partners, and PCB ODMs.
  • Knowledge of ML and LLM architectures, accelerator architectures, or HPC system design.
  • Startup experience or comfort working in fast-paced environments.

Culture & Benefits

  • Fully in-person engineering team based in San Jose.
  • Medical, dental, and vision coverage, plus a $500 monthly credit for waiving medical benefits.
  • $2,000 monthly housing subsidy for employees living within walking distance of the office.
  • Wellness benefits, daily lunch and dinner, and an unlimited compute budget subject to ROI justification.
  • Relocation support for moves to San Jose.
  • Technical staff contribute across engineering and research disciplines.

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