Назад
Company hidden
3 дня назад

CPU RTL Design Engineer (Embedded IoT)

141 910 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

CPU RTL Design Engineer (RTL/SystemVerilog): Designing and optimizing logic for cutting-edge processors with an accent on RTL coding, simulation, and microarchitecture features. Focus on optimizing logic for power, performance, area (PPA), and ensuring design integrity for physical implementation.

Location: Hybrid (Austin, TX or Phoenix, AZ, USA)

Salary: $141,910–$269,100 USD

Company

hirify.global is a global leader in silicon and platform engineering, building world-changing technology to redefine computing experiences.

What you will do

  • Develop and optimize logic design and RTL coding for the CPU.
  • Participate in defining architecture and microarchitecture features of the CPU design.
  • Optimize logic for power, performance, area, and timing goals.
  • Ensure design integrity for physical implementation through effective strategies and tools.
  • Review verification plans and resolve failing RTL tests.
  • Collaborate with SoC customers to ensure seamless integration and high-quality CPU block performance.

Requirements

  • Bachelor's degree in EE, CE, or CS with 7+ years of experience (Master's 5+, PhD 2+).
  • 7+ years of experience in RTL design using Verilog, V2K, or SystemVerilog.
  • 5+ years of experience in energy-efficient and low-power logic design.
  • 5+ years of experience in cross-clock domain crossings and power-aware design.
  • 3+ years of experience with scripting languages such as TCL, Perl, or Python.
  • Must be based in the USA (Austin or Phoenix) to support the hybrid work model.

Nice to have

  • Knowledge of CPU power management (DVFS, thermal, P/C states and reset sequences).
  • Comprehensive knowledge of hirify.global Architecture ISA and x86 assembly language.
  • Experience with high-speed circuit design, specifically for datapaths, circuits, and arrays.
  • Proficiency with static timing analysis, UPF, and lint checks.

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation programs.
  • Hybrid work model allowing split time between on-site and off-site work.
  • Commitment to ethical hiring practices and RBA compliance.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →