CPU Core Physical Design Engineer (VLSI)

TL;DR

CPU Core Physical Design Engineer (VLSI): Performing physical design implementation of custom CPU designs from RTL to GDS with an accent on synthesis, place and route, and static timing analysis. Focus on optimizing CPU design for power, frequency, and area to power the AI revolution.

Location: Hybrid in Folsom, California, US

Salary: $105,650.00 - 200,340.00

Company

hirify.global is a global technology leader shaping the future of AI, analytics, and cloud-to-edge technology through breakthrough silicon and platform solutions.

What you will do

• Implement custom CPU designs from RTL to GDS, including synthesis, place and route, clock tree synthesis, and floor planning.
• Conduct verification and signoff, including formal equivalence verification, static timing analysis, and power integrity.
• Collaborate with logic, circuit, architecture, and design automation teams to recommend improvements for CPU microarchitectures.
• Partner with EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPUs.
• Optimize product-level parameters such as power, frequency, and area while improving physical design methodologies.

Requirements

• Bachelor's degree in Computer Engineering, CS, Electrical/Electronic Engineering, or STEM with 2+ years of experience, OR a Master's degree with 1+ year of experience.
• 1+ years of experience in VLSI circuit design and synthesis.
• 1+ years of experience in Static Timing Analysis (STA).
• 1+ years of experience in Low power design.
• Must be based in or able to work hybrid in Folsom, California, US.

Nice to have

• Experience with x86 CPU architecture.
• Proficiency in Tcl, Perl, or Python programming.

Culture & Benefits

• Total rewards package including competitive pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing a split between on-site and off-site work.