Memory Interface PHY IP, Design Engineering Architect (Memory Interface PHY IP)

Location: San Jose, California, United States

Annual salary: $136,500–$253,500, plus potential bonus, equity, and benefits.

Company

hirify.global develops technology products and intellectual property for the semiconductor industry.

What you will do

• Develop PHY architectures for memory interface IP, including DDR and LPDDR.
• Make architecture decisions covering electrical, timing, power, protocol, and JEDEC compliance requirements.
• Guide TX/RX, clocking, termination, power delivery, and signal integrity trade-offs.
• Serve as a customer-facing technical architect during pre-sales, evaluations, post-delivery support, and feature customization.
• Collaborate with Sales, Marketing, Program, design, verification, layout, and silicon validation teams.
• Review architecture specifications and design reviews, document technical decisions, and influence product and technology roadmaps.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 15 years of industry experience in memory interface PHY, high-speed I/O, or related domains.
• Strong knowledge of memory interface PHYs, JEDEC standards, and protocols.
• Experience owning customer-facing technical engagements and driving issues to closure.
• Excellent written and verbal communication skills.

Culture & Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential eligibility for incentive compensation, including bonus and equity.