High Speed PHY System Architect (Analog Mixed-Signal)

TL;DR

High Speed PHY System Architect (Analog Mixed-Signal): Developing analog and mixed-signal IP architectures and calibration algorithms for SoC independent AMS IPs with an accent on signal processing and transistor-level feasibility. Focus on designing next-generation AMS IP to optimize performance, power, and area across diverse product segments.

Location: Hybrid; Must be based in Santa Clara, CA or Hillsboro, OR (USA)

Salary: $164,470.00 - $311,890.00 USD

Company

hirify.global's Central Engineering Group (CEG) is a data-driven organization building scalable engineering solutions for IP, custom ASICs, and foundry enablement.

What you will do

• Develop analog and mixed-signal IP architectures, signal processing, and calibration algorithms for SoC independent AMS IPs.
• Conduct top-down architectural analysis and transistor-level feasibility studies for AMS circuits.
• Design novel microarchitectures for next-generation AMS IP to optimize performance, power, and area.
• Enhance system performance using digitally assisted analog techniques and optimized analog-digital partitioning.
• Collaborate with IP design and verification teams to validate robust AMS IPs for SoC integration.
• Define future technology targets by influencing cross-functional roadmaps and reviewing emerging trends.

Requirements

• Bachelor's degree in Electrical Engineering or related STEM field with 9+ years of experience (or Master's with 6+ / PhD with 3+).
• Experience in analog and mixed-signal circuit design (op-amps, comparators, bandgap references, linear regulators) within CMOS technologies.
• Proficiency with backend verification tools such as Monte Carlo simulations, EMIR, and MOSFET voltage checks.
• Hands-on experience with transmission line theory and AMS system modeling.
• Proven experience with high-speed PHY designs from concept through qualification.
• Must be based in the United States (California or Oregon).

Nice to have

• Proficiency in MATLAB or similar tool-based modeling.
• Experience in post-silicon debugging and high-volume productization of designs.
• Familiarity with signal integrity and power integrity analysis.
• Background in analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization.

Culture & Benefits

• Total compensation package including competitive pay and stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Hybrid work model allowing employees to split time between on-site and off-site work.