Senior Engineer, Packaging Engineering (FIB)

Location: Batu Kawan, Malaysia; Penang SDSM Office

Company

hirify.global develops Flash memory and advanced memory technology solutions supported by global manufacturing capabilities.

What you will do

• Develop and maintain package recipe and process baselines based on failure analysis findings.
• Perform device-level physical failure analysis using SEM and FIB, including cross-sectioning, delayering, and defect localization.
• Analyze device structures, interfaces, and failure mechanisms to identify packaging and reliability issues.
• Lead package evaluation and qualification for NAND and ASIC technologies.
• Collaborate with wafer fabrication, package design, assembly R&D, characterization, and process engineering teams.
• Provide failure analysis recommendations to support chip structure optimization and package and product design decisions.

Requirements

• Bachelor’s degree or above in Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or a related discipline.
• More than 3 years of hands-on SEM and FIB experience is mandatory.
• Solid experience in physical failure analysis of semiconductor devices.
• Strong understanding of device structures, packaging architectures, and failure mechanisms.
• Good English communication skills, written and spoken.
• Ability to work effectively in cross-functional, global teams.

Nice to have

• Background in wafer fab processes and device design.
• Experience with NAND or ASIC technologies.
• Familiarity with electrical and physical characterization methods.
• Knowledge of assembly processes and advanced semiconductor packaging.
• Experience supporting fab or package process change qualification.

Culture & Benefits

• Full-time exempt position.
• Inclusive environment focused on diversity, respect, belonging, and contribution.
• Accessibility support is available throughout the application and hiring process.