Design Engineer - STA (VLSI/ASIC)

Location: Fort Collins, Colorado, USA; onsite at 4380 Ziegler Road

Salary: USD 129,400–207,000 annual base salary

Company

hirify.global is hiring for a semiconductor design engineering role focused on static timing analysis.

What you will do

• Analyze significant and unique development and support issues involving VLSI and ASIC physical design constraints and implementation techniques.
• Create, debug, and review timing constraints, timing reports, warning messages, and error messages in static timing analysis tools.
• Perform setup, hold, signal integrity, crosstalk delay, glitch/noise, RC network, and other timing analyses.
• Coordinate with engineers and teams across geographies, organize large datasets, and present technical findings clearly.
• Independently determine methods for new or special assignments, manage multiple tasks, and develop solutions to debugging problems.
• Collaborate with supervisors and may supervise the activities of others.

Requirements

• BS in Electrical Engineering or Computer Engineering with 12+ years of related experience, or MS in Electrical Engineering or Computer Engineering with 10+ years of related experience.
• Strong understanding of VLSI and ASIC physical design.
• Basic understanding of PLLs, clock networks, flip-flops, latches, memories, and basic CMOS logic gates.
• Experience using a static timing analysis tool, preferably Synopsys PrimeTime and/or Cadence Tempus.
• Understanding of RC networks, signal propagation, signal integrity, crosstalk delay, glitch/noise analysis, setup analysis, hold analysis, timing checks, and timing diagrams.
• TCL coding experience is required. Python, Ruby, and Bash are listed programming languages; experience with one or two additional coding languages is preferred.
• Ability to communicate clearly with multiple engineers and teams, organize and present large amounts of data, manage varied tasks, debug problems, and exercise strong engineering judgment.
• Professional, open, and highly self-motivated attitude.

Nice to have

• Understanding of POCV/SOCV/LVF variation modeling, MIS, CCS/ECSM/NLDM liberty timing models, PBA, and LOCV/SOCV location-aware timing derates.
• Experience with timing SOIC/3DIC designs.
• Experience using SPICE analysis.
• Experience with one or two coding languages in addition to TCL.

Culture & Benefits

• Full-time employment with independent work on new or special assignments and close collaboration with a supervisor.
• Discretionary annual bonus and eligibility for new-hire and annual equity awards, subject to plan documents and award agreements.
• Medical, dental, and vision plans; 401(k) participation with company matching; and an Employee Stock Purchase Program.
• Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leaves.

Hiring process

• First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
• Applicants located outside the USA should provide a home address for future correspondence.