2 дня назад
Design Engineer - STA
129 400 - 207 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Engineer - STA (VLSI/ASIC): Developing and supporting static timing analysis for VLSI and ASIC physical designs with an accent on timing constraints, signal integrity, clock networks, and timing-model variation. Focus on debugging timing-tool warnings and reports, analyzing setup and hold behavior, creating timing diagrams, and solving complex timing problems across geographically distributed engineering teams.
Location: Fort Collins, Colorado, USA
Salary: USD 129,400–207,000 annual base salary, plus discretionary annual bonus and equity awards.
Company
develops semiconductor and technology solutions.
What you will do
- Perform static timing analysis for VLSI and ASIC physical designs.
- Create and debug timing constraints and analyze timing-tool warnings, errors, and reports.
- Evaluate setup, hold, signal integrity, crosstalk delay, glitch, and noise behavior.
- Analyze RC networks, clock networks, PLL-related timing, and timing diagrams.
- Collaborate and communicate with engineers and teams across geographical time zones.
- Organize, present, and manage large amounts of timing data while debugging complex problems.
Requirements
- BS in Electrical Engineering or Computer Engineering with 12+ years of related experience, or MS with 10+ years of related experience.
- Strong understanding of VLSI and ASIC physical design, including flip-flops, latches, memories, CMOS logic gates, PLLs, and clock networks.
- Experience with a static timing analysis tool, preferably Synopsys PrimeTime or Cadence Tempus.
- Solid understanding of setup and hold analysis, RC networks, signal integrity, crosstalk, glitch/noise analysis, and timing checks.
- TCL is required; programming experience with Python, Ruby, or BASH is listed for the role.
- Ability to work independently, manage multiple tasks, debug issues, and communicate clearly with geographically distributed teams.
Nice to have
- Understanding of POCV, SOCV, LVF, MIS, CCS, ECSM, NLDM, PBA, and location-aware timing derates.
- Experience timing SOIC or 3DIC designs.
- Experience with SPICE analysis.
- Ability to supervise the activities of others.
Culture & Benefits
- Independent work on significant and unique development and support issues.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation time, and applicable paid family and other leave.
- Employee Assistance Program and professional, open, self-motivated work environment.
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