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44 минуты назад

Principal Engineer-Design (Digital Design)

75 000 - 232 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Digital Design Engineer (ASIC/SoC, Verilog/SystemVerilog): Leading digital IP and SoC-level integration for mixed-signal microcontrollers from concept through tape-out with an accent on RTL design, verification, low-power intent, and signoff coordination. Focus on developing reusable digital peripherals, closing timing, power, DRC, and LVS issues, and coordinating complex integration work across analog, physical design, architecture, validation, and product teams.

Location: Chandler, Arizona, United States

Annual base salary: $75,000–$232,000

Company

hirify.global develops semiconductor products and technologies for applications that power systems worldwide.

What you will do

  • Own digital block and subsystem design from concept through tape-out.
  • Develop reusable Verilog and SystemVerilog RTL for digital peripherals and IP blocks.
  • Lead block- and SoC-level verification, integration, simulation regressions, assertions, and coverage.
  • Integrate and verify UPF low-power intent and collaborate on AMS and mixed-signal verification.
  • Coordinate STA, power and IR analysis, synthesis handoff, physical design collaboration, and timing, DRC, LVS, and ECO closure.
  • Provide technical leadership through design reviews, documentation, debugging, and project planning.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of ASIC/SoC digital design and verification experience.
  • Strong knowledge of digital logic, finite-state machine design, computer architecture, RTL coding, and SoC integration.
  • Working knowledge of physical design and APR flows, including synthesis, floorplanning, place-and-route, CTS, ECO, and timing, power, and DFM closure.
  • Experience with industry EDA flows and tools such as Cadence, Synopsys, or Siemens, plus Linux and Windows.
  • Scripting skills in Python, Perl, or Tcl for productivity and flow automation.
  • Strong debugging, analytical, communication, ownership, and cross-functional collaboration skills.

Nice to have

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Culture & Benefits

  • Full-time position with a team-oriented, fast-paced environment.
  • Health benefits begin on the first day.
  • Retirement savings plans and an employee stock purchase program with a two-year lookback feature.
  • Total compensation includes base pay, restricted stock units, and quarterly bonus payments.
  • Travel expectation is 0%–25%; the role involves primarily sitting, with some walking and standing.

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