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Principal Engineer-Design (Digital ASIC/SoC)

75 000 - 232 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Engineer-Design (Digital ASIC/SoC): Leading digital IP and SoC-level integration for mixed-signal microcontrollers with an accent on RTL design, verification, low-power integration, and signoff closure. Focus on developing reusable Verilog/SystemVerilog blocks, coordinating timing, power, physical-design, and mixed-signal verification, and driving designs through tape-out.

Location: Chandler, Arizona, United States; onsite role with 0%–25% travel.

Annual base salary: $75,000–$232,000 USD, plus restricted stock units and quarterly bonus payments.

Company

hirify.global is a large semiconductor technology company developing products and solutions that power electronic systems worldwide.

What you will do

  • Own digital block and subsystem design from concept through tape-out, partnering with architects and system engineers on requirements.
  • Develop reusable Verilog and SystemVerilog RTL for 8- and 32-bit digital peripherals and IP.
  • Lead block- and SoC-level verification, simulation, regressions, assertions, coverage, UPF integration, and low-power verification.
  • Coordinate AMS and mixed-signal verification with analog teams, plus STA, power, IR, synthesis, and physical-design signoff activities.
  • Support floorplanning, place-and-route, timing, DRC/LVS closure, ECOs, and implementation handoffs with physical-design teams.
  • Provide technical leadership through design reviews, documentation, debugging, project planning, and cross-functional collaboration with architecture, product, test, applications, and marketing teams.

Requirements

  • B.S. in Electrical Engineering, Computer Engineering, or a related field and 10+ years of experience in ASIC/SoC digital design and verification.
  • Strong foundations in digital logic, finite-state-machine design, computer architecture, RTL coding, and SoC integration.
  • Working knowledge of physical design and APR flows, including synthesis, floorplanning, place-and-route, CTS, ECOs, and timing, power, and DFM closure.
  • Familiarity with Cadence, Synopsys, or Siemens EDA flows and tools, as well as Linux and Windows.
  • Scripting skills in Python, Perl, or Tcl for productivity and flow automation.
  • Excellent debugging, analytical-thinking, and communication skills, with the ability to drive alignment across teams.
  • Ability to work in a team-oriented, fast-paced environment with ownership and continuous-learning mindset.
  • Physical requirements include hearing, seeing, talking, approximately 80% sitting, 10% walking, and 10% standing.

Nice to have

  • M.S. in Electrical Engineering, Computer Engineering, or a related field.

Culture & Benefits

  • Values-based environment emphasizing trust, empowerment, respect, diversity, communication, and community.
  • Employee development supported through Leadership Passage Programs and continuous learning opportunities.
  • Health benefits begin on the first day.
  • Retirement savings plans and an employee stock purchase plan with a two-year look-back feature.
  • Compensation package includes competitive base pay, restricted stock units, and quarterly bonus payments.

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