pythonperlverilogsystemveriloglow power designtclstatic timing analysisprimetimetiming closuretempus
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$161к-298к/год
$180к$210кмедиана$220к
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Понятная senior-роль в известной компании полупроводниковой отрасли: обязанности конкретны, а пакет льгот сильный. При этом требования предполагают высокий уровень опыта.
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Высокий порог входаАктуальные инструментыЩедрый пакет льготСильная компания
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Текст:
Hirify AI/Оригинал
TL;DR
Static Timing Analysis Engineer (Low-Power Wireless SoCs): Developing timing constraints and timing-closure signoff for complex low-power wireless SoCs and mixed-signal IP systems with an accent on asynchronous clock networks, timing corners, and signoff methodology. Focus on improving static timing analysis flows, scripting timing-report analysis, and resolving complex timing issues across IP, SoC, and multifunctional design teams.
Location: Hybrid, Austin, Texas, United States
Salary: $160,650–$298,350 annual base pay
Company
hirify.global develops low-power wireless connectivity and embedded technologies for smart home, industrial IoT, and smart city applications.
What you will do
Develop timing constraints at IP and SoC levels in collaboration with designers.
Improve static timing analysis flows and methodologies.
Develop timing signoff criteria covering aging, on-chip variation, and signal integrity.
Analyze timing reports with scripting to generate insights and accelerate timing closure.
Resolve complex static timing issues with a global design team.
Drive timing closure for mixed-signal IP integration with multifunctional teams.
Requirements
Bachelor’s or master’s degree in electrical or computer engineering and 8+ years of experience.
In-depth knowledge of timing-closure flows and methodologies.
Experience developing timing constraints for functional and test modes, including scan.
Hands-on experience with static timing tools such as Tempus or PrimeTime.
In-depth knowledge of Perl, Python, Tcl, and shell scripting.
Knowledge of timing-closure modes and corners, low-power design methodologies, including static and dynamic clock gating, power gating, and dynamic voltage and frequency scaling.
Knowledge of timing-model generation for mixed-signal IP.
Knowledge of design flows including Lint, CDC, synthesis, logic equivalence, DFT, and place and route.
Knowledge of Verilog and SystemVerilog.
Culture & Benefits
Hybrid work arrangement in Austin.
Medical, dental, and vision plans, including PPO or consumer-driven plans with HSA.
401(k) matching, Roth plan option, equity rewards, life and disability coverage, and flexible spending accounts.
Flexible PTO, three paid volunteer days annually, charitable contribution matching, and tuition reimbursement.
Adoption assistance, backup childcare, commuter and legal benefits, pet insurance, downtown parking, onsite gym, and wellness offerings.
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