Synthesis & STA Engineer – High-Speed SerDes

Location: San Jose, California, United States

Salary: $160,000–$200,000 per year, plus potential discretionary bonuses, equity incentives, and comprehensive benefits.

Company

hirify.global develops semiconductor-based connectivity solutions and software for AI and cloud infrastructure, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Drive RTL synthesis and area, power, and timing optimization for digital controller and DSP blocks in high-speed SerDes PHY designs.
• Develop and validate SDC constraints, including clock definitions, generated clocks, multi-mode and multi-frequency constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions.
• Set up and manage MMMC static timing analysis across process, voltage, and temperature corners, driving timing closure from synthesis through sign-off.
• Define I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.
• Perform block- and full-chip timing analysis, root-cause debugging, ECO guidance, and timing ECO generation for SerDes digital logic.
• Develop automation, partitioning, and resource-efficient flows; collaborate with analog, RTL, physical design, architecture, implementation, and verification teams on clock trees, power domains, and PLL/CDR-generated clocks.

Requirements

• Bachelor's degree in Electrical Engineering or Computer Science.
• At least 8 years of experience in synthesis, timing-constraint development, STA, and sign-off for high-speed mixed-signal IP in server, storage, networking, or SerDes applications.
• Strong proficiency writing and debugging SDC constraints, including clock modeling, generated clocks, clock-domain crossings, and exception handling.
• Expertise in STA methodology and timing closure at block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence-checking flows using Formality and/or Conformal at advanced nodes, including 5nm/3nm and below.
• Proficiency with Cadence and/or Synopsys physical-design and STA toolchains.
• Strong scripting ability in Tcl, Python, and Perl.
• Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Nice to have

• Direct experience with high-speed SerDes, Ethernet PHY 112G/224G, or PCIe/CXL PHY digital-controller and DSP timing challenges.
• Understanding of analog/mixed-signal integration, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation-cell constraints.
• Knowledge of ECO methodologies, DFT tools, and test-coverage analysis for mixed-signal designs.
• Experience integrating RTL and hard macros from IP vendors, including Liberty, LEF, and behavioral-model characterization.
• SystemVerilog/Verilog proficiency.
• Familiarity with power-aware synthesis and STA using UPF/CPF flows.
• Experience with high-speed clocking architectures and multi-rate clock-domain management in SerDes designs.
• Master's degree in Electrical Engineering or Computer Science.

Culture & Benefits

• Comprehensive benefits are available.
• The role may include discretionary bonuses and equity incentives.
• The company encourages applications from people with diverse backgrounds and experiences.