VLSI Physical Design / APR Engineer

Location: Hsinchu, Taiwan

Company

Developing AI vision processors for edge applications that extract valuable data from high-resolution video streams.

What you will do

• Implement full-chip and block-level physical design from netlist to tape-out and GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis, routing, and layout verification.
• Collaborate with front-end design, DFT, and package teams to achieve design closure.
• Conduct sign-off analysis covering static timing, signal integrity, power integrity, reliability, and manufacturability.
• Analyze and resolve congestion, timing, power integrity, and signal integrity issues.
• Develop and maintain Tcl-based physical design automation scripts and implementation flows while coordinating with EDA vendors and foundries.

Requirements

• Master’s degree in electrical engineering, computer engineering, computer science, or a related field.
• 2–7 years of experience in the VLSI field.
• Experience with tape-out of multi-million-gate SoC designs.
• Strong skills with at least one Cadence, Synopsys, or Mentor EDA tool.
• Experience with design methodologies, flow deployment and refinement, and technical problem solving.
• Strong communication, teamwork, initiative, innovation, and ability to learn quickly.

Nice to have

• Experience with 10 nm, 7 nm, 5 nm, or 3 nm designs.
• Perl or Tcl scripting experience.
• Proficiency in spoken and written English.

Culture & Benefits

• Full-time employment.
• Cross-functional collaboration with front-end design, DFT, package, EDA vendor, and foundry teams.