Senior Staff Engineer (ASIC/VLSI Synthesis)

TL;DR

Senior Staff Engineer (ASIC/VLSI Synthesis): Developing and validating timing constraints and front-end implementation flows for complex SoC designs with an accent on synthesis, STA, and timing closure. Focus on optimizing power, performance, and area (PPA) for high-speed silicon in advanced technology nodes like 5nm/4nm.

Location: Must be based in San Diego, CA

Salary: $135,900 - $201,130 per annum

Company

hirify.global is a leader in semiconductor solutions, providing essential building blocks for data infrastructure across cloud, AI, and enterprise architectures.

What you will do

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to define timing modes and constraints.
• Own front-end implementation tasks including synthesis, UPF development, and functional ECOs.
• Analyze power, performance, and area tradeoffs to drive chip implementation.
• Perform physical-aware synthesis using industry-standard tools like Fusion Compiler.
• Automate front-end flows using Tcl or Python scripting.

Requirements

• Must be eligible to access export-controlled information under U.S. law.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field.
• Minimum 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Hands-on experience with synthesis, STA methodologies, and timing closure.
• Proficiency in Tcl, Perl, or Python scripting.
• Experience with advanced technology nodes (e.g., TSMC N4/N5).

Culture & Benefits

• Comprehensive financial well-being programs including employee stock purchase plan.
• Robust mental and physical health resources.
• Family support programs to balance work and home life.
• Recognition and service awards for contributions and milestones.