Principal Engineer (ASIC)

TL;DR

Principal Engineer (ASIC): Developing state-of-the-art IC solutions utilizing leading-edge CMOS cell-based ASIC technologies with an accent on 5nm/3nm designs. Focus on full chip synthesis, STA, and physical design implementation including floor planning and design closure.

Location: China-Shanghai-Zhangjiang Hi Tech

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Develop state-of-the-art IC solutions utilizing leading-edge CMOS cell-based ASIC technologies.
• Manage ASIC designs through all development phases, including RTL analysis, synthesis, design optimization, and timing verification.
• Execute full chip synthesis flows (DC, DCT, DCG) specifically for 5nm/3nm design tape out.
• Implement physical design tasks including floor planning, placement, design closure, and DRC & LVS checks.
• Perform full chip STA and constraint clean-up flows.
• Conduct simulation, test insertion, vector generation, and post-prototype test support.

Requirements

• Solid VLSI background and a deep understanding of the ASIC design flow.
• Proven experience with tapeout in 5nm and below process designs.
• Ability to handle block implementation and top-level tasks independently.
• Strong communication and problem-solving skills.
• MS degree in Microelectronics or a related discipline.

Nice to have

• Experience with DFT insertion and Power/IVD analysis.
• Expertise in DRC/LVS, Top Floorplan, STA, and Low Power design.
• Proficiency in Perl, Tcl, or Python.

Culture & Benefits

• Opportunity to work on the latest 5nm/3nm cutting-edge designs.
• Collaborative team environment with opportunities for professional career growth.
• Equal opportunity employer commitment.