Physical IC Design Engineer (AI/ML)

TL;DR

Physical IC Design Engineer (AI/ML): Designing and implementing next-generation AI and ML ecosystems through PCIe Switch and Enterprise Storage products with an accent on RTL to silicon tape-out. Focus on timing closure, synthesis, and physical verification to ensure world-class performance in mega datacenters.

Location: Must work in person at the San Jose site; no remote work allowed.

Salary: $143,800 - $230,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions, focusing on high-performance AI, ML, and enterprise storage technologies.

What you will do

• Execute the full physical design cycle from RTL to silicon tape-out.
• Perform synthesis, physical verification, and timing closure using various strategies.
• Conduct EM/IR analysis, Place and Route, and Clock Tree Synthesis.
• Develop and optimize design flows and methodologies.
• Collaborate closely with RTL engineers to refine chip architecture.
• Manage floor-planning and layout for high-performance ASIC products.

Requirements

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• 12+ years of relevant experience in physical IC design.
• Proficiency in TCL/PERL scripting and industry-standard EDA tools.
• Hands-on experience across the full physical design cycle (RTL to Tape-out).
• Must be based in or be able to work on-site in San Jose, CA.
• Excellent verbal and written communication skills.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company-paid holidays.
• Access to Employee Assistance Program (EAP).