ASIC Physical Design Engineer (SoC)

TL;DR

ASIC Physical Design Engineer (SoC): Implementing SOC devices from RTL to GDSII for next-generation products with an accent on timing, power, and area optimization. Focus on executing place-and-route, performing static timing analysis, and driving physical signoff for manufacturable tapeout-ready designs.

Location: Onsite in Louisville, CO or Beaverton, OR (USA). Candidates must be U.S. Persons or be prepared to secure U.S. government export authorizations (ITAR).

Salary: $148,900 – $276,500

Company

hirify.global, a subsidiary of Ralliant Corporation, provides precision-engineered measurement solutions to eliminate barriers between inspiration and realization of world-changing technologies.

What you will do

• Execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII, including floor-planning and routing.
• Drive place-and-route execution using industry-standard EDA tools to optimize timing, power, area, and signal integrity.
• Perform static timing analysis (STA) and timing verification across multiple modes and corners to achieve timing closure.
• Support physical signoff activities, including DRC, LVS, formal equivalence checking, and IR drop analysis.
• Collaborate with RTL design, verification, DFT, analog, and packaging teams to ensure tapeout-ready designs.
• Develop and maintain scripts and flows to improve physical design automation and methodology.

Requirements

• BS in Electrical Engineering or equivalent experience.
• 5+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
• Working knowledge of RTL-to-GDSII physical design flows and ability to resolve congestion and signal integrity issues.
• Proficiency with industry-standard tools from Cadence, Synopsys, or Siemens EDA.
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Must be a U.S. Person (citizen, lawful permanent resident, or protected individual) or obtain ITAR export authorization.

Nice to have

• 10+ years of hands-on ASIC physical design experience.
• MS or PhD in Electrical Engineering.
• Principal-level experience leading physical design for complex ASIC or SoC programs.
• Advanced expertise in SoC-level timing closure and clocking methodology.
• Demonstrated technical leadership managing internal execution and external design service providers.

Culture & Benefits

• Inclusive engineering culture focused on continuous growth and learning.
• Customer-obsessed approach to conceptualizing and delivering high-impact solutions.
• Eligible for a bonus as part of the total compensation package.
• Commitment to diversity and inclusion through the "We Are More Together" vision.