Назад
Company hidden
1 день назад

Senior FPGA Engineer (Algo)

150 000 - 250 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Europe/Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Senior FPGA Engineer (Algo) (FPGA/Verilog): Building a low-latency, high-throughput FPGA application for a trading team with an accent on RTL design, hardware-software interaction, and complete FPGA development flow ownership. Focus on architecting new FPGA systems from requirements through production, solving hardware limitations, and performing synthesis, place and route, static timing analysis, and lab debugging.

Location: Chicago office only, United States

Salary: $150,000–$250,000 annual base salary, plus an annual discretionary bonus.

Company

hirify.global is a diversified trading firm using proprietary technology and capital across financial markets and non-traditional strategies, including cryptoassets.

What you will do

  • Architect and implement FPGA applications from the ground up for a trading team.
  • Own synthesis, place and route, static timing analysis, and technical documentation.
  • Research and evaluate FPGA hardware and emerging technologies.
  • Develop solutions to overcome FPGA and hardware limitations.
  • Collaborate directly with software and other design teams throughout the development lifecycle.
  • Perform system and block-level testing, lab debugging, and characterization of new hardware.

Requirements

  • Bachelor’s degree or higher in Computer or Electrical Engineering, with 3+ years of relevant experience; a Master’s degree or higher may count toward experience.
  • Strong hardware engineering experience, especially with FPGA systems.
  • 2+ years of experience writing Verilog and strong RTL logic design and verification skills.
  • Experience with synthesis, place and route, and static timing analysis.
  • Experience designing system-on-chip architectures, memory and processor subsystems, networking, and peripheral interconnects.
  • Knowledge of TCP/IP and strong working knowledge of either Xilinx or Altera FPGA design flow.

Nice to have

  • Functional verification experience using high-level methodologies such as SystemVerilog.
  • Excellent research and data-gathering skills.

Culture & Benefits

  • High-autonomy environment with an emphasis on innovation, integrity, and challenging consensus.
  • Opportunity to build an FPGA application from scratch for an existing trading team.
  • Medical, pharmacy, dental, and vision insurance.
  • 401(k) with discretionary employer match, disability and life insurance, health savings accounts, and flexible spending accounts.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →