Senior FPGA Design Engineer (AI Security)

Location: San Jose, CA, USA

Salary: USD 150,000–200,000 yearly

Company

hirify.global develops semiconductor, silicon, and systems solutions for secure AI-driven digital infrastructure, including its Trusted Control/Compute Unit technology for data centers, cloud platforms, and 5G systems.

What you will do

• Design FPGA RTL, including RTL porting, IP integration, timing closure, and bitstream generation.
• Set up and run FPGA simulations and testing.
• Set up, validate, and debug FPGA systems.
• Collaborate with software engineers to bring up and validate FPGA-based products.
• Work with Architecture, Verification, ASIC Design, and Software teams on system integration.

Requirements

• At least 5 years of industrial engineering experience.
• Strong experience in RTL design for FPGAs and FPGA product development.
• Experience with Vivado, Protocompiler, RTL simulation, IP and CPU integration, and FPGA system bring-up and debugging.
• Familiarity with PCIe, USB, Ethernet, and SPI.
• BS or MS degree in EE, EECS, CS, or an equivalent qualification.
• Self-driven approach, strong problem-solving ability, and effective communication skills.

Nice to have

• Experience with ESPI, SGPIO, or LTPI.

Culture & Benefits

• Work in a diverse, collaborative environment focused on curiosity, execution, respect, and continuous learning.
• Contribute to security and reliability solutions for critical digital infrastructure.
• Join a well-funded Silicon Valley semiconductor company working with Tier 1 industry partners.
• Equal opportunity employment environment.