Назад
Company hidden
5 дней назад

Product Physical Failure Analysis Engineer (Semiconductor)

149 100 - 215 925$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Product Physical Failure Analysis Engineer (Semiconductor): Identifying root causes of semiconductor device failures, yield issues, reliability risks, and customer returns with an accent on physical analysis, fault isolation, and semiconductor materials and device interactions. Focus on executing FIB, SEM, and EDX investigations, interpreting emission microscopy, laser voltage probing, and OBIRCH data, and driving corrective actions for next-generation FPGA products and packages.

Location: San Jose, California, United States; onsite, Shift 1.

Salary: $149,100–$215,925 USD annually for the Bay Area, plus incentive opportunities.

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

  • Identify root causes of semiconductor device failures, yield issues, reliability risks, and customer returns.
  • Collaborate with product, yield, reliability, fault isolation, design, and process development engineers.
  • Define and execute physical failure analysis using die milling, FIB, SEM, and EDX.
  • Interpret emission microscopy, laser voltage probing, and OBIRCH data to isolate faults.
  • Develop FMEA, maintain control plans, and improve failure analysis processes and automation.
  • Document findings, communicate reports, and recommend corrective actions to prevent recurrence.

Requirements

  • BS degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or a related field.
  • 8+ years of semiconductor failure analysis experience.
  • 8+ years of experience with layout and design tools such as Virtuoso, Avalon, and SysNav.
  • 8+ years of independently implementing die milling/thinning, FIB layer-by-layer deprocessing, SEM, and EDX analysis.
  • 8+ years of driving investigations to root cause and improving yield and reliability.
  • Applicants must be eligible for required U.S. export authorizations.

Nice to have

  • Understanding of FPGA architecture and design-for-test features.
  • Experience with Teradyne Ultraflex testers.
  • Experience in semiconductor packaging failure analysis.

Culture & Benefits

  • Work in an independent FPGA company focused on speed, innovation, and close customer partnerships.
  • Collaborate across product development, manufacturing, design, and reliability functions.
  • Incentive opportunities are tied to individual and company performance.
  • Equal employment consideration is provided in accordance with applicable law.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →