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Quantum Bump Integration Engineer (Quantum Packaging)

98 000 - 176 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Quantum Bump Integration Engineer (Quantum Packaging): Developing cryogenic, superconducting bumping processes and end-to-end interconnect integration for scalable quantum hardware packaging with an accent on bump metallurgy, wafer-level processing, and 2.5D/3D architectures. Focus on establishing process windows at millikelvin-to-kelvin temperatures, improving yield and manufacturability, and characterizing low-loss, low-thermal-leakage interconnects for quantum systems.

Location: Essex Junction, United States

Salary: $98,000–$176,000 per year

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services across a global manufacturing footprint.

What you will do

  • Develop cryogenic-compatible bump interconnect technologies using indium, SnAg, Cu pillar, and superconducting metals.
  • Define and optimize bump structures, metallurgy, process flows, and integration schemes for superconducting packaging.
  • Own wafer-level bump integration through assembly, qualification, and transition from R&D to pilot or high-volume manufacturing.
  • Establish process windows for electrical, thermal, and mechanical stability at millikelvin-to-kelvin temperatures.
  • Improve yield, defectivity, reliability, and manufacturability through DOE, statistical analysis, and root-cause investigations.
  • Collaborate with qubit, cryogenic systems, packaging, assembly, modeling, reliability, test, design, vendor, and OSAT teams.

Requirements

  • Master’s degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or a related field.
  • At least 8 years of related professional experience with a master’s degree.
  • In-depth knowledge of BEOL processes, bump and wafer-finish integration, wafer test and probe, OSAT collaboration, package development, and assembly.
  • Strong problem-solving, technical troubleshooting, and design-of-experiments skills.
  • Overall GPA of at least 3.0 and good academic standing.
  • Written and verbal English fluency required; travel of up to 10%.

Nice to have

  • PhD education level with at least 5 years of related experience.
  • Prior leadership, project management, planning, organizational, and communication experience.

Culture & Benefits

  • Work with advanced packaging and photonics technologies for scalable quantum hardware.
  • Collaborate with multidisciplinary internal teams, external partners, tool suppliers, vendors, and OSAT providers.
  • Contribute to invention disclosures, publications, conference presentations, process specifications, and integration guidelines.
  • Equal opportunity workplace with a focus on diversity, inclusion, and respectful collaboration.
  • Employment is subject to applicable background checks, medical screenings, and local laws.

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