Sort Interface Pathfinding and Development Engineer (Advanced Packaging)

Location: On-site in Hillsboro, Oregon, United States

Annual salary: $133,800–$255,200 USD

Company

hirify.global develops semiconductor technologies across computing, connectivity, artificial hirify.globalligence, advanced packaging, testing, and manufacturing.

What you will do

• Develop silicon interface probing and test solutions for wafer and die sort across advanced process nodes and heterogeneous packaging platforms, including EMIB, EMIB-T, Foveros, and Foveros Direct.
• Design and execute experiments to optimize probing technologies, contact architectures, probing margins, yield, and process health.
• Translate chiplet and package requirements into scalable sort interface specifications for Foundry and OSAT customers.
• Create sort design rules and Interface Design Kits for external fabless customers and design partners.
• Architect test interface hardware with customer design and DFT teams and resolve technical gaps.
• Lead supplier pathfinding, technical co-design, hardware delivery, and manufacturing readiness for new product introductions.

Requirements

• Bachelor’s degree in electrical engineering, mechanical engineering, materials science, or a related STEM field plus 6+ years of industry experience; or a master’s degree plus 4+ years; or a Ph.D. plus 2+ years of relevant experience.
• Experience with wafer or die sort technology, prober-tester cell integration, and advanced probe card qualification.
• Experience structuring and executing design of experiments for probing margins, yield, and process health.
• Experience with ATE test hardware or methodology, sort/class product development, or PCB, space transformer, or substrate design rules and stackup architectures.
• Strong collaboration, communication, analytical problem-solving, initiative, and customer-facing skills.

Nice to have

• Advanced probing process characterization and supplier relationship management experience.
• Knowledge of OSAT or Foundry test operations, multi-client test cell standards, customer design collateral, PDK enablement, or turnkey test delivery models.
• Experience with fine-pitch micro-bumps, 2.5D/3D architectures, silicon bridges, or wafer-level chip-scale probing.
• Hands-on experience with Advantest V93k or Teradyne Ultra-FLEX.

Culture & Benefits

• Cross-functional collaboration with customers, global suppliers, design teams, and test solution vendors.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Work model requires on-site presence.