Quantum IC Substrate Package Layout Design Engineer

Location: On-site in Hillsboro, Oregon, United States

Annual salary: $122,440–$172,860 USD

Company

Intel's Quantum Computing Group develops silicon-based quantum processors using spin qubits in silicon quantum dots and advanced semiconductor manufacturing.

What you will do

• Design large form factor IC substrates using Siemens Xpedition.
• Collaborate with silicon testchip, signal integrity, power integrity, thermal simulation, and system integration engineers.
• Validate and verify designs, including DRC and LVS checks.
• Integrate IC substrates with advanced 2.5D and 3D packaging architectures.
• Coordinate design tapeout with substrate suppliers and Intel substrate teams.
• Present designs, document milestones, and track developments in packaging technology.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or a related field and 5+ years of relevant experience, or an M.S. degree and 3+ years of relevant experience.
• Experience designing IC substrates for CPU, GPU, SoC/ASIC, or related architectures.
• Experience with Siemens Xpedition design environments and workflows.
• Experience with high-speed signal routing and large form factor IC substrates.
• Strong analytical, problem-solving, communication, presentation, and cross-functional collaboration skills.
• On-site availability in Hillsboro, Oregon, United States is required.

Nice to have

• Experience with advanced routing engines, including AI- or physics/model-based routing.
• Understanding of signal integrity, power integrity, and thermal effects on IC substrate design.

Culture & Benefits

• Work in a multidisciplinary quantum computing research environment.
• Collaborate with research divisions and academic institutions.
• Competitive pay, stock bonuses, health benefits, retirement programs, and vacation.
• Opportunities to follow advances in packaging technology through conferences and technical papers.