Senior/Staff Design Engineer (RISC-V)

Location: Santa Clara, United States; onsite

Expected salary range: $69,000.00–$202,000.00 per year

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services, including RISC-V CPU IP and AI-enabled processors through its MIPS team.

What you will do

• Drive the microarchitecture and RTL design of critical blocks for an AI-enabled RISC-V CPU core.
• Design RISC-V vector CPU functionality, custom extensions, and an AI-enabled matrix engine.
• Develop and refine design features and RTL against power, performance, area, timing, reliability, testability, and safety goals.
• Perform architectural exploration, microarchitectural research, specification development, and high-performance strategy analysis with the CPU modeling team.
• Support functional verification, verification strategy, and assessment of RTL performance goals.
• Collaborate with a multifunctional engineering team on physical design implementation and validation.

Requirements

• Knowledge of pipeline stages in an in-order or out-of-order high-performance CPU core.
• Knowledge of microprocessor architecture, including one or more of instruction fetch and decode, branch prediction, instruction scheduling, register renaming, reorder buffers, out-of-order execution, integer and floating-point execution, load/store execution, instruction and data prefetch, vector datapaths, or cache and memory subsystems.
• Knowledge of SystemVerilog, Verilog, and/or VHDL.
• Experience with simulators and waveform debugging tools.
• Knowledge of logic design principles and their timing and power implications.
• Bachelor’s degree with 3–7 years of experience or Master’s degree with 2–5 years of experience.

Nice to have

• Experience designing RISC-V, ARM, and/or MIPS CPUs.
• Experience with hardware multithreading, virtualization, and SIMD designs.
• Experience with vector- and matrix-enabled CPUs, preferably RISC-V processors.
• Understanding of high-performance and low-power microarchitecture techniques and trade-offs.
• Experience using a scripting language such as Perl or Python.
• Knowledge of cache coherency and memory consistency.
• Understanding of CPU integration at the SoC level.
• Understanding of safety and security microarchitecture.

Culture & Benefits

• Full-time employment with hirify.global.
• Commitment to equal opportunity and workplace diversity.
• Work must be performed safely and responsibly in accordance with Environmental, Health, Safety, and Security requirements.
• Reasonable accommodations are available during the employment process.