Founding RTL Design Engineer (AI Inference ASIC)

Location: Full-time onsite in the South Bay, San Francisco Bay Area, United States

Salary: $250,000–$400,000 cash compensation plus meaningful early-stage equity

Company

Seed-funded stealth company building a dedicated LLM inference chip and the software stack around it, with Stanford AI researchers and silicon engineers from NVIDIA, Groq, and Google.

What you will do

• Implement and debug RTL for a purpose-built inference ASIC.
• Translate microarchitecture into digital logic and own a defined chip component from design through implementation and debugging.
• Solve complex logic and microarchitecture problems.
• Work with verification engineers to establish correctness and resolve design issues.
• Collaborate with physical implementation teams to address design constraints.
• Work directly with founders and experienced silicon engineers to iterate and deliver the first inference chip.

Requirements

• Strong personal ownership of RTL implementation for a digital ASIC or SoC.
• Evidence of solving difficult logic or microarchitecture problems through personal implementation.
• Experience working with verification and implementation teams to resolve design issues.
• Ability to explain technical decisions, tradeoffs, and individual contributions in depth.
• Staff, Senior Staff, or Principal-level technical depth. Exceptional engineers earlier in their careers may also be considered.
• Enthusiasm for detailed, hands-on engineering in a small founding team.
• Comfort taking ownership and delivering independently in an early-stage environment.
• Willingness to work full-time onsite in the South Bay.

Nice to have

• Inference ASIC or AI accelerator experience.
• Strong adjacent experience with digital ASIC, SoC, or compute silicon.

Culture & Benefits

• High-ownership role with the opportunity to build a meaningful part of the first chip.
• Direct collaboration with founders and experienced silicon engineers.
• Early-stage equity included in the compensation package.
• Hands-on work in a small founding engineering team.