RTL Design Engineer (AI)

Location: Palo Alto Office, USA

Company

hirify.global develops world models and AI agents for learning, evaluation, planning, experimentation, and interaction with the physical world, with an initial focus on hardware, electronics systems, and semiconductors.

What you will do

• Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
• Drive production-silicon designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
• Partner with verification and formal teams on test plans, assertions, and coverage closure.
• Debug complex functional and timing issues across simulation, emulation, and silicon.
• Review and evaluate AI-generated RTL and help define correct, high-quality design practices.
• Work directly with customer design teams when needed.

Requirements

• 5+ years of RTL design experience on chips that have taped out.
• Expertise in SystemVerilog and Verilog, with strong microarchitecture skills.
• Hands-on experience with lint, CDC, synthesis, and timing-aware design.
• Familiarity with common protocols such as AXI, PCIe, Ethernet, DDR, or similar.
• Experience with Python or Tcl scripting.

Nice to have

• Experience writing SVA or working with formal verification.
• Experience with low-power design, including UPF, clock gating, and power gating.
• Interest in AI-assisted design tools.

Culture & Benefits

• Work with leading semiconductor companies on real chip programs.
• Collaborate with a team backed by Silicon Valley investors, Stanford University, and senior semiconductor and technology leaders.