R&D Engineer IC Design 5 (ASIC Verification)

Location: San Jose, California, USA; onsite at 1320 Ridder Park Drive

Annual base salary: USD 143,800–230,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops semiconductor and infrastructure technology products, including high-performance networking solutions.

What you will do

• Develop complex verification environments for high-performance network switch ASICs and FPGAs.
• Create comprehensive verification test plans and execute hands-on implementation across ASIC verification activities.
• Architect testbenches and drive verification through full closure.
• Collaborate with system architects, design engineers, and verification teams.
• Support ASIC design and verification cycles from initial concept through production.

Requirements

• 8+ years of ASIC design and verification experience.
• Bachelor’s degree in Engineering.
• Complete understanding of Verilog and hands-on C/C++ experience.
• Strong knowledge of object-oriented programming and modern ASIC verification flows, including UVM and SystemVerilog.
• Experience with ASIC design flows for deep sub-micron technologies and multiple ASIC tape-outs, including at least one project taken from concept through full production.
• Fully comfortable with technical and business English for documentation, cross-functional collaboration, and executive communications.

Nice to have

• Networking background and experience with Ethernet, PCIe, routing, or switching protocols.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
• Discretionary annual bonus, competitive new-hire equity grant, and annual equity awards.