R&D Engineer IC Design 5 (ASIC)

TL;DR

R&D Engineer IC Design 5 (ASIC): Developing complex verification environments and test plans for high-performance network switch ASICs/FPGAs with an accent on system-level verification and closure. Focus on architecting testbenches, implementing UVM/SystemVerilog flows, and ensuring hardware reliability through multiple tape-out cycles.

Location: San Jose, California, USA

Salary: USD 143,800 - 230,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Develop complex verification environments and comprehensive test plans for high-performance network switch ASICs/FPGAs.
• Implement ASIC verification across all stages, collaborating closely with system architects and design engineers.
• Architect testbenches and drive verification closure from initial concept through full production.
• Verify high-performance networking hardware to ensure system stability and reliability.

Requirements

• 8+ years of ASIC design/verification experience.
• Must be based in or authorized to work in the USA.
• Strong proficiency in Verilog, C/C++, and object-oriented programming (OOP).
• Expertise in modern ASIC verification flows, specifically UVM and SystemVerilog.
• Proven track record of completing multiple ASIC tape-outs.
• English: C1 level (technical and business fluency) required.

Nice to have

• Experience with networking protocols such as Ethernet, PCIe, and routing/switching.

Culture & Benefits

• Competitive annual base salary with discretionary annual bonuses.
• New hire equity grants and annual equity awards.
• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching and Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company paid holidays.