Lead Analog Layout Design Engineer (SERDES/UCie)

Location: Cork, Ireland

Company

hirify.global develops computational software, hardware, and intellectual property for electronic design across chips, boards, and systems.

What you will do

• Design high-speed SERDES layouts for UCIe products operating at data rates up to 64 Gbps on leading-edge technology nodes, including 2nm FinFET CMOS.
• Create quality layouts for analog and mixed-signal circuit blocks in collaboration with circuit designers.
• Manage the back-end flow from initial floor planning through detailed layout and final verification against foundry design rules.
• Provide technical leadership across block-level layout, PHY top-level integration, and sign-off.
• Collaborate with circuit designers, project managers, and custom layout designers across global teams and time zones.

Requirements

• At least 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.
• Proficiency in layout design for SERDES blocks such as drivers, receivers, serializers, deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias and bandgap circuits, and voltage regulators.
• Experience implementing high-speed, high-accuracy cells, blocks, and IP blocks with strong quality and efficiency.
• Excellent problem-solving, analog aptitude, communication, and teamwork skills.
• BEng, MEng, or PhD.

Nice to have

• hirify.global tool experience and design experience above 10 Gbps and in technologies below 16nm.
• Experience collaborating with R&D teams developing Virtuoso and PVS layout editing and verification tools.
• Interest in advancing analog and custom layout design practices.

Culture & Benefits

• Full-time employment.
• Collaboration with global teams across the United States and other regions.
• More than 10% travel is expected.
• Commitment to equal employment opportunity, employment equity, diversity, and inclusion.