Analog Layout Engineer (Semiconductors)

TL;DR

Analog Layout Engineer (Semiconductors): Developing block-level and IP-level analog/RF layouts for advanced semiconductor nodes with an accent on FinFET and deep sub-micron processes. Focus on floorplanning, routing, and optimization for complex modules such as SerDes, ADC/DACs, and PLLs.

Location: Onsite in San Francisco or Santa Clara, USA

Salary: $97,700 – $203,800 per year

Company

hirify.global is a global business and technology transformation partner helping organizations accelerate their transition to a digital and sustainable world.

What you will do

• Develop block-level and IP-level analog/RF layouts, driving designs from concept to tape-out.
• Own floorplanning, placement, routing, and optimization for complex analog and mixed-signal blocks (SerDes, ADC/DACs, PLLs).
• Lead top-level integration of multiple analog and mixed-signal blocks within larger SoCs.
• Apply expertise in deep sub-micron and FinFET process technologies, considering EM, ESD, and reliability.
• Resolve complex DRC, LVS, antenna, and verification issues.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics, or a related field.
• 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred).
• Proven experience with analog floor planning for high-speed or precision circuits like SerDes, ADC/DAC, and PLLs.
• Strong understanding of layout best practices for deep sub-micron CMOS and FinFET technologies.
• Must be based in or able to work onsite in San Francisco or Santa Clara.

Culture & Benefits

• Paid time off including 12-25 days of vacation depending on grade, sick leave, and company holidays.
• Comprehensive medical, dental, and vision coverage.
• Retirement savings plans such as 401(k) in the U.S.
• Life and disability insurance.
• Employee assistance programs and a collaborative global community.