Principal Analog Layout Engineer (Semiconductor)

TL;DR

Principal Analog Layout Engineer (Semiconductor): Drawing and optimizing complex layouts for high-speed SerDes IPs in deep sub-micron FinFET technologies with an accent on physical verification and circuit design collaboration. Focus on shaping the technical DNA of the new San Diego design organization and ensuring high-quality silicon production.

Location: Must be based in San Diego, CA

Salary: $152,300–$225,440 per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential infrastructure for data, cloud, and AI architectures.

What you will do

• Create layouts for schematics using industry-standard CAD tools in deep sub-micron FinFET processes.
• Collaborate with Circuit Design Engineers to clarify requirements and implement necessary schematic modifications.
• Perform physical verification including DRC, LVS, ANT, ERC, and EMIR analysis to achieve closure.
• Contribute to the technical strategy and culture of the expanding San Diego design team.
• Work effectively across functional teams and remote design groups.

Requirements

• Bachelor’s degree with 15+ years, Master’s with 10-12 years, or PhD with 8-10 years of relevant experience.
• Must be eligible to access export-controlled information under U.S. law.
• Proficiency in Cadence Virtuoso VXL or Synopsys Custom Compiler.
• Experience with Mentor Graphics Calibre for verification.
• Strong communication and problem-solving skills.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust mental and physical health resources.
• Family support programs to assist with work-life balance.
• Recognition and service awards for professional contributions.