Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$160к-245к/год
$160к$190кмедиана$220к
По похожим ролям (46) ~ $190к/год
На СНГ рынке: $1.7к/мес ($1.4к - $3к)
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Крутая вакансия
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Чёткая ответственность за верификацию до tapeout, фокус на энергоэффективном AI-железе и влияние на растущий стартап делают вакансию сильной, но нужен серьёзный опыт на senior-уровне.
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Актуальный стекЖелезо для AIВлияние на продуктВысокий порог опыта
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Staff Digital Verification Engineer (ASIC/SoC): Driving functional verification of complex SoC and IP designs from specification through tapeout with an accent on UVM/SystemVerilog environments, constrained-random verification, coverage closure, and Python automation. Focus on debugging complex simulation failures, signing off multi-million-gate designs, and coordinating verification risks and tradeoffs across technical and program teams.
Location: San Francisco Bay Area, Pittsburgh, PA, or Austin, TX
Base salary: $160,000–$245,000 annually, plus a 10% annual bonus and equity.
Company
hirify.global develops energy-efficient computing architecture and processors for AI, autonomous machines, intelligent infrastructure, wearables, space systems, and edge computing.
What you will do
Drive functional verification of complex SoC and IP designs from specification through tapeout.
Own verification across multiple full cycles, from testbench architecture through tapeout sign-off.
Build and develop UVM-based testbench environments and constrained-random verification flows.
Drive functional and code coverage closure for complex, multi-million-gate SoC and ASIC designs.
Debug complex simulation failures and develop Python-based test automation, log analysis, coverage post-processing, and regression flows.
Communicate verification risks, status, and tradeoffs to technical peers and program leadership.
Requirements
Bachelor’s or Master’s/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of progressive experience in ASIC/SoC design verification, including multiple full ownership cycles from testbench architecture through tapeout.
Expertise in UVM-based testbench architecture and constrained-random verification methodology.
Experience with C/C++ for modeling or verification.
Demonstrated experience driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
Ability to debug complex simulation failures.
Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
Ability to clearly communicate verification risk, status, and tradeoffs to technical peers and program leadership.
Nice to have
Experience in formal verification using JasperGold or a similar tool.
Experience building or using AI agentic flows for design verification.
Software- or firmware-based testing experience and collaboration with software teams before silicon.
Post-silicon experience.
Understanding of and experience with processors such as ARM or RISC-V, AMBA AXI/ACE/CHI interconnects, memory controllers, DMA engines, interrupt controllers, and standard peripherals.
Experience with power-aware verification and UPF.
Culture & Benefits
Opportunity to take ownership and influence products and verification processes during the transition from early development to market release and volume production.
Competitive base salary, annual bonus, meaningful equity, and comprehensive benefits.
401(k) match and company-paid benefits.
Paid parental leave and flexibility.
Opportunities to grow technical skills and career as the company scales.
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