ASIC Design Engineer (Networking Chips)

Location: Onsite at an HPE office; salary information is specified for the United States, including California

Salary: $120,000–$243,000 annual base salary in California, United States. Variable incentives may also be offered.

Company

hirify.global develops edge-to-cloud technology and advanced networking routers, switches, and silicon.

What you will do

• Develop detailed micro-architecture specifications from functional module requirements while meeting power and area targets.
• Implement ASIC designs using Verilog and SystemVerilog.
• Write functional coverage and SVA to help identify corner-case bugs.
• Collaborate with Physical Design on floorplanning and timing closure, including fixing RTL timing issues to meet frequency targets.
• Work with Verification to fully validate design blocks.
• Mentor new college graduates and interns.

Requirements

• Bachelor’s degree in Electrical Engineering and 4+ years of relevant experience.
• Strong analytical and problem-solving skills.
• Strong Verilog/SystemVerilog coding experience from coursework, projects, or professional work.
• Knowledge of synthesis, lint, and other EDA tools.
• Knowledge of computer architecture and networking protocols is beneficial.
• Excellent written and verbal communication skills.

Nice to have

• Master’s degree in Electrical Engineering.
• Perl or Python knowledge.
• Experience with AI agentic tools.

Culture & Benefits

• Benefits support physical, financial, and emotional wellbeing.
• Professional development programs support career growth and expertise building.
• Inclusive culture that values varied backgrounds and individual uniqueness.
• Flexible support for managing work and personal needs.