ASIC Design Engineer 2 (SystemVerilog)

Location: Onsite at an HPE office; United States salary range specified for California

Salary: USD 105,500–213,500 annual base salary in California, United States. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud technology company developing infrastructure, networking, and data solutions.

What you will do

• Develop high-speed networking ASICs from functional specifications through final netlists.
• Define detailed micro-architecture specifications for assigned modules with guidance from senior engineers.
• Write synthesizable RTL using Verilog and SystemVerilog.
• Develop functional coverage and SystemVerilog Assertions.
• Perform timing closure with the physical design team and resolve timing issues in RTL.
• Debug block-level issues identified by the verification team and use EDA tools for design checks.

Requirements

• Bachelor’s degree in Electrical Engineering; a Master’s degree is strongly preferred.
• Coursework in digital logic design.
• Strong analytical and problem-solving skills.
• Strong Verilog/SystemVerilog coding skills demonstrated through coursework or internship projects.
• Written and verbal communication skills.

Nice to have

• Knowledge of computer architecture, networking protocols, or machine learning through graduate-level coursework.
• Knowledge of Perl or Python.

Culture & Benefits

• Health, financial, and emotional wellbeing benefits.
• Personal and professional development programs supporting career growth.
• Inclusive workplace focused on diversity, innovation, teamwork, and customer success.
• Flexibility to manage work and personal needs within an onsite work arrangement.