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6 часов назад

Senior Technical Staff-Design (Signal and Power Integrity)

91 000 - 232 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Technical Staff-Design (Signal and Power Integrity) (high-speed FPGA and SerDes): Developing and driving signal and power integrity methodologies for high-speed FPGA products with an accent on die, package, and board-level analysis, PDN optimization, and channel modeling. Focus on building pre- and post-layout simulations, solving crosstalk and jitter challenges, optimizing 32G+ SerDes transceivers, and guiding SIPI engineers.

Location: San Jose, California, United States; onsite

Annual base salary: $91,000–$232,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global develops embedded control and semiconductor products, including microcontrollers, FPGAs, mixed-signal and power management devices, connectivity products, and memory solutions.

What you will do

  • Develop and drive signal and power integrity methodologies for high-speed FPGA products.
  • Perform pre-layout and post-layout SIPI simulations across die, package, and board levels.
  • Analyze channel loss, eye diagrams, jitter, crosstalk, PDN performance, and SerDes equalization.
  • Influence die, package, and board design decisions based on simulation and correlation results.
  • Collaborate with global cross-functional teams, suppliers, external partners, and customers.
  • Provide technical guidance and mentorship to SIPI engineers while improving tools and design methodologies.

Requirements

  • BS degree in Electrical Engineering, Electronic Engineering, or a related field.
  • 15+ years of relevant experience, including 10+ years of hands-on signal and power integrity experience.
  • Extensive PCB design, layout, manufacturing, package analysis, and system-level SIPI experience.
  • Experience with high-speed SerDes, including troubleshooting channel issues for 32G transceivers and beyond.
  • Expertise in PDN optimization, S-parameter extraction, channel modeling, via and stack-up analysis, TDR, eye diagrams, jitter, and equalization.
  • Hands-on experience with Ansys HFSS, Ansys Siwave, Mentor Graphics HyperLynx, HSPICE, RedHawk, Keysight ADS, VNAs, TDRs, oscilloscopes, and BERTs.

Nice to have

  • Experience with IBIS-AMI modeling, validation, and correlation.
  • MS degree in a relevant engineering field.
  • Experience with package thermal and mechanical analysis.

Culture & Benefits

  • Health benefits begin on the first day.
  • Retirement savings plans and an employee stock purchase program with a two-year lookback feature.
  • Competitive base pay, restricted stock units, and quarterly bonus payments.
  • Travel expectation is 0%–25%; work is performed indoors during usual business hours.

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