Senior Technical Staff-Design (Signal and Power Integrity)

Location: San Jose, California, United States. The role is based at 3850 N. First St and includes 0%–25% travel.

Annual base salary: $91,000–$232,000. Total compensation also includes restricted stock units and quarterly bonus payments.

Company

hirify.global develops embedded control and semiconductor products, including microcontrollers, microprocessors, FPGAs, mixed-signal and power-management devices, connectivity products, and memory solutions.

What you will do

• Develop and drive signal and power integrity methodologies for high-speed FPGA products across die, package, board, and system levels.
• Perform pre-layout and post-layout SIPI simulations, including PDN and transceiver co-simulations, to optimize product performance.
• Analyze channel loss, eye diagrams, jitter, crosstalk, equalization, return loss, insertion loss, and other high-speed SerDes impairments.
• Influence die, package, and board design decisions based on simulation, correlation, and debugging results.
• Collaborate with global cross-functional teams, external partners, suppliers, and customers on SI/PI topics.
• Provide technical guidance and mentorship while developing tools, methodologies, and processes that improve SIPI design efficiency.

Requirements

• Bachelor of Science degree in Electrical Engineering or Electronic Engineering.
• 15+ years of relevant experience, including 10+ years of practical, hands-on Signal Integrity and Power Integrity experience.
• Practical experience with PCB design and layout principles, PCB manufacturing processes, and system-level SIPI methodologies across die, package, and board levels.
• Experience resolving SI/PI challenges, including PDN optimization, noise mitigation, and system-level topology construction for PDN and transceiver co-simulations.
• In-depth knowledge of S-parameter extraction, system-level channel modeling, via modeling, connector TDR analysis, stack-up analysis, equalization, jitter, and eye-diagram analysis.
• Hands-on experience with Ansys HFSS, Ansys Siwave, Mentor Graphics HyperLynx, HSPICE, and Redhawk field solvers, plus Keysight ADS and Mentor Graphics HyperLynx for pre- and post-layout simulation.
• Hands-on experience with VNAs, TDRs, sampling and real-time oscilloscopes, BERTs, de-embedding techniques, and jitter-analysis equipment.
• Strong analytical, debugging, problem-solving, verbal, and written communication skills.

Nice to have

• High-speed SerDes experience, especially troubleshooting channel-related issues for 32G transceivers and beyond.
• Experience with package analysis and optimization, including thermal and mechanical considerations.
• Experience with IBIS-AMI modeling, validation, and correlation.
• Master of Science degree in a relevant engineering field.

Culture & Benefits

• Full-time employment within a global, cross-functional organization.
• Health benefits beginning on the first day.
• Retirement savings plans and an employee stock purchase program with a two-year look-back feature.
• Restricted stock units and quarterly bonus payments as part of total compensation.
• Indoor work during usual business hours; approximately 80% sitting, 10% standing, and 10% walking.