Principal Hardware Engineer (Semiconductor)

Location: Santa Clara, CA, United States; onsite role.

Expected base pay: $150,680–$225,700 per annum, plus eligibility for bonus and equity plans.

Company

Semiconductor solutions provider developing infrastructure technologies for enterprise, cloud, AI, carrier, data center, network security, and high-speed connectivity applications.

What you will do

• Lead high-density, high-volume board and system designs from concept through production, including custom ASIC solutions built on 3nm technology and high-speed SerDes.
• Design and review board-level systems, schematics, and layouts for storage, network security, and custom ASIC applications, emphasizing signal integrity, power integrity, and cost optimization.
• Work with hardware, software, silicon, firmware, system, board development, DVT, and SI teams to test, debug, resolve, and close product issues.
• Manage designs with JDM partners, provide design guidance, support build readiness, and ensure production quality.
• Provide technical support to strategic customers, including design discussions, documentation, presentations, failure debugging, and product integration.
• Conduct design reviews, facilitate technical discussions, and provide technical leadership throughout the product development cycle.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of related professional experience, or a Master’s degree and/or PhD with 5–10 years of experience.
• At least 5 years of experience designing high-speed digital circuitry on complex, high-density PCB assemblies, including Ethernet controllers, microcontrollers, and processors.
• At least 5 years of experience working with ODMs.
• At least 5 years of experience designing high-density boards with fine-pitch components and microvias.
• Expertise in high-speed interfaces including DDR4/5, PCIe Gen5+, 100G Ethernet, QSPI, and USB, using medium- to high-end CPUs.
• Good knowledge of power supply design and hands-on measurement experience.
• Good debugging skills and experience using laboratory equipment.
• Expertise in designing for optimal signal and power integrity.
• Customer-facing experience with excellent verbal and written communication skills; understanding of mechanical components and their use in board design; familiarity with Cadence Allegro schematic and layout tools.
• Critical-thinking, problem-solving, ownership, detail orientation, and the ability to support ideas with facts.

Nice to have

• Basic Linux proficiency for system test environment setup.

Culture & Benefits

• Work on infrastructure semiconductor products for AI data centers, network security, storage, and high-speed connectivity.
• Employee stock purchase plan with a two-year look-back.
• Bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Family support programs, mental and physical health resources, and recognition and service awards.
• Employment is subject to applicable U.S. export control and eligibility requirements for access to export-controlled technology.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills without the use of AI assistance or automated note-taking tools.
• Reasonable accommodations are available during the selection process upon request.