Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$181к-367к/год
$180к$200кмедиана$230к
По похожим ролям (50) ~ $200к/год
88
Крутая вакансия
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Чётко очерченная инженерная роль в крупной сетевой компании даёт возможность работать с высокоскоростными SerDes и сильной профильной командой, но требует глубокой экспертизы и работы из офиса.
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Работа в офисеСовременная экспертизаЧёткие задачиСильная команда
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Signal Integrity Engineer (PAM4 SerDes): Developing and validating high-speed ASIC PAM4 SerDes and system-level signal and power integrity solutions for networking products with an accent on channel modeling, timing analysis, and design margin optimization. Focus on correlating simulations with board measurements, tuning serial links up to 200G, and implementing SI rules across ASIC packages, PCBs, and connectors.
Location: Onsite in Sunnyvale, California, United States
Base salary: USD 181,000–367,000 annually in California; variable incentives may also be offered.
Company
Global edge-to-cloud technology organization developing networking, data, and application solutions.
What you will do
Perform COM channel margin analysis and develop ASIC PAM4 SerDes channel simulation models for ASIC packages, boards, and connectors.
Correlate ASIC PAM4 SerDes simulations with measurements and collaborate with component and ASIC vendors to improve model accuracy.
Perform PCB timing analysis and define, document, and implement signal-integrity layout rules and checklists.
Tune ASIC PAM4 SerDes parameters to improve serial-link design margins.
Perform SI DVT board measurements, correlate results with simulations, and provide technical assessments to the SI management team.
Requirements
10+ years of signal integrity analysis experience with a bachelor's degree in Electrical Engineering, Computer Engineering, Microwave Engineering, and/or RF Engineering; or 8+ years of signal integrity analysis experience with a master's degree in one of these fields.
Required experience with 56G/112G ASIC PAM4 SerDes technologies.
Hands-on experience with serial channels up to 200G line rates, including coefficient tuning and TP1A measurements.
Strong ability to debug and resolve ASIC PAM4 SerDes and channel performance issues.
Good oral and written communication skills, ability to collaborate across geographies in a matrix organization, and ability to work on several projects simultaneously.
Nice to have
Experience with 200G ASIC PAM4.
Proficiency with Ansys HFSS, SIwave, ADS, Allegro, Sigrity, and MATLAB.
Proficiency with oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, and phase-noise analyzers; laboratory debugging skills.
Experience with system-clock design and PLL design and debugging.
Experience designing PCB stack-ups using 2-D field solvers.
Culture & Benefits
Onsite work primarily from an office.
Health and wellbeing benefits supporting employees and their families.
Personal and professional development programs supporting career growth and expertise building.
Inclusive workplace with flexibility to manage work and personal needs.
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