Technical Staff Engineer – Analog Design (Networking)
Контакты
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
ethernetusbverilogadcserdescadence virtuosomixed signal designplldacanalog ic design
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Роль четко определена с ясным акцентом на аналоговое проектирование для высокоскоростных интерфейсов, но отсутствие информации о зарплате затрудняет оценку общей привлекательности.
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Текст:
Hirify AI/Оригинал
TL;DR
Technical Staff Engineer – Analog Design (Networking) (Analog IC/SERDES): Designing and developing analog and mixed-signal integrated circuits for next-generation Ethernet and USB products with an accent on high-speed Datacom SERDES macros, transistor-level verification, and post-silicon validation. Focus on architecting complex analog sub-blocks, optimizing parasitic and proximity effects, and coordinating cross-functional design and validation activities.
Location: Chandler, Arizona, United States; onsite role with 0%–25% travel
Company
hirify.global is a large semiconductor technology company developing Ethernet, USB, and other integrated circuit products.
What you will do
Define architectures and block-level specifications for high-speed Datacom Ethernet and USB SERDES.
Design and verify analog and mixed-signal macros, including ADCs, DACs, PLLs, transmitters, receivers, LDOs, regulators, high-speed I/Os, bandgaps, POR circuits, oscillators, charge pumps, protection circuits, switching converters, and analog switches.
Perform system- and transistor-level mixed-mode simulations across operating scenarios, process corners, and mismatch conditions.
Develop schematics, behavioral models, design specifications, and validation plans using Cadence Virtuoso and related tools.
Collaborate with layout and cross-functional engineering teams to optimize parasitic effects, interfaces, and implementation details.
Lead design reviews, document designs, and support post-silicon ATE and laboratory validation.
Requirements
BSEE and at least 15 years of industry experience in Electronics or Electrical Engineering.
Demonstrated experience designing multiple analog SERDES sub-blocks, including ADCs, DACs, PLLs, transmitters, receivers, LDOs, regulators, high-speed I/Os, bandgaps, POR circuits, oscillators, charge pumps, protection circuits, DC-DC switching converters, and analog switches.
Strong expertise in low-power and high-speed design techniques, device physics, complex system analysis, and mixed-signal simulation.
Experience architecting high-speed interfaces such as PCIe, Ethernet, and USB.
Extensive experience with Cadence and other analog/mixed-signal IC design tools, including proficiency in Cadence Virtuoso.
Hands-on laboratory validation experience with power supplies, source meters, oscilloscopes, signal generators, and related equipment.
Experience with DRC, LVS, ERC, PEX, EM analysis, SOA verification, aging analysis, and SHE effects.
Experience with Unix/Linux and scripts such as Scheme, SKILL, Perl, or Tcl.
Strong verbal, written, technical, communication, analytical, interpersonal, collaboration, organization, and continuous-learning skills; ability to manage multiple complex tasks, meet aggressive timelines, and work with minimal supervision.
Experience working in globally distributed design teams.
Nice to have
Knowledge of Verilog, Liberty timing models, and IBIS-AMI models.
Culture & Benefits
Full-time employment within a large global organization.
Work is performed indoors, primarily sitting, with regular collaboration and independent work.
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