Analog Layout Engineer (eInfochips)

Location: Austin, USA; remote locations listed in Texas, California, and Minnesota. The role is described as fully onsite and may require travel to an Arrow client office; remote employees may be required to attend the closest designated Arrow office. Working hours follow the US Central Time Zone.

Company

eInfochips, an hirify.global company, provides product engineering and semiconductor design services across multiple industries and countries.

What you will do

• Design physical silicon layouts for high-frequency and high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and other high-speed blocks.
• Create block-level and chip-top-level floor plans and manage hierarchical block integration.
• Handle micro-bump and package-aware co-design.
• Address layout-dependent effects, device matching, common-centroid structures, guard rings, isolation, and shielding.

Requirements

• 5–12+ years of hands-on custom IC layout experience.
• Experience with deep sub-micron or advanced CMOS/FinFET nodes, such as TSMC N3, N5, or N7.
• Critical experience with lower nodes, especially N3 or N5.
• Experience with reliability and verification closure for DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
• Bachelor’s degree.
• Ability to travel to an Arrow client office location when requested by client leadership.

Culture & Benefits

• Full-time employment within Arrow’s engineering services organization.
• Remote work may be available from specified US locations, subject to office attendance requirements.
• Arrow is an equal opportunity employer.