Senior Staff Digital Design Engineer (Verilog/SystemVerilog)
Контакты
135 900 - 201 130$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
dspverilogcdcsystemverilogsynthesisrtl designtiming closuredigital ic design
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$136к-201к/год
$160к$170кмедиана$190к
По похожим ролям (50) ~ $170к/год
87
Хорошая вакансия
развернуть
Роль четко описана и предполагает ответственность за ключевые блоки в разработке чипов для дата-центров и ИИ-инфраструктуры; при этом важно учитывать проверку на доступ к технологиям, подпадающим под экспортный контроль.
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Экспортный контрольАктуальные технологииИИ-инфраструктураОтветственность за блок
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior Staff Digital Design Engineer (Verilog/SystemVerilog): Developing synthesizable RTL for digital IP blocks and subsystems supporting data-center connectivity and AI infrastructure with an accent on timing, area, power, and low-power design checks. Focus on translating architectures into RTL, resolving timing-closure and model-to-hardware correlation issues, and validating designs through simulation, emulation, FPGA prototyping, and silicon bring-up.
Location: Irvine, CA, United States
Expected base pay: $135,900–$201,130 per annum
Company
hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, and data infrastructure architectures.
What you will do
Develop RTL designs using Verilog/SystemVerilog for digital IP blocks and subsystems.
Translate architectural specifications into clean, synthesizable RTL.
Perform linting, clock-domain crossing, and low-power design checks.
Analyze timing, area, and power tradeoffs; support synthesis and collaborate with physical design teams on timing closure.
Debug functional issues found during simulation, emulation, FPGA prototyping, or silicon bring-up.
Investigate model-to-hardware correlation issues and participate in silicon validation.
Requirements
Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 5–10+ years of related professional experience, or a Master’s degree and/or PhD in these fields with 3+ years of experience.
Independently analyze and optimize small sub-circuit blocks across Process, Voltage, and Temperature.
Serve as the responsible engineer for at least one major sub-circuit block from architecture definition through fine tuning.
Identify and propose innovative solutions to improve at least one major sub-circuit block.
Participate in root-cause investigations and silicon validation of model-to-hardware correlation issues.
Mentor and coach new or less experienced team members.
Nice to have
Knowledge of communication and DSP algorithms.
Verification experience, with UVM experience preferred.
Culture & Benefits
Work within the Connectivity business group focused on communication, data centers, and AI infrastructure.
Collaborate on technology used by chip companies and large technology companies.
Base pay is supplemented by bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
Benefits include an employee stock purchase plan with a two-year lookback, family support programs, mental health resources, and recognition and service awards.
The role may involve access to export-controlled technology and may require export license review.
Hiring process
Interviews are intended to assess individual experience, thought process, and communication skills.
AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.
Reasonable accommodations are available during the selection process.
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